# US 12,002,761 B2 · Semiconductor device, stacked semiconductor device and manufacturing method of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,761 B2 - Document ID: US12002761B2 - Status: Granted - Kind: B2 - Application number: 17/884,579 - Filed: 2022-08-10 - Published: 2022-12-01 - Granted: 2024-06-04 - Earliest claimed: 2020-05-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chih-Hang Tung; Chen-Hua Yu; Tung-Liang Shao; Su-Chun Yang; Wen-Lin Shih - Web page: https://patentgrep.com/patent/US12002761B2 ## CPC - H10W 40/25: characterised by their materials - H10W 70/611: {for connecting multiple chips together} - H10W 20/032: {of conductive barrier, adhesion or liner layers} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/081: {by forming openings in the dielectric parts} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 72/019: {of bond pads} - H10W 72/07236: {Soldering or alloying} - H10W 72/921: {Structures or relative sizes of bond pads} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/941: {Dispositions of bond pads} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/301: {Bonding techniques, e.g. hybrid bonding} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/333: {Compression bonding} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; an electrical insulating and thermal conductive layer disposed over the semiconductor substrate; a dielectric structure disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure; and a circuit layer damascened in the dielectric structure, wherein the circuit layer comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the electrical insulating and thermal conductive layer is substantially coplanar with the bottom surface of the circuit layer. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein a material of the electrical insulating and thermal conductive layer comprises boron nitride (h-BN) or aluminum nitride (AlN). ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, further comprising an etch stop layer disposed over the electrical insulating and thermal conductive layer, wherein the thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the etch stop layer. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, further comprising an etch stop layer disposed beneath the electrical insulating and thermal conductive layer, wherein the thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the etch stop layer. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein the dielectric structure comprises a lower dielectric layer disposed over the electrical insulating and thermal conductive layer and an upper dielectric layer disposed over the lower dielectric layer. ### Claim 6 (depends on 5) The semiconductor device as claimed in claim 5, further comprising an electrical insulating and thermal conductive interlayer disposed between the lower dielectric layer and the upper dielectric layer, wherein a thermal conductivity of the electrical insulating and thermal conductive interlayer is substantially greater than a thermal conductivity of the dielectric structure. ### Claim 7 (depends on 6) The semiconductor device as claimed in claim 6, wherein a part of the circuit layer extend through electrical insulating and thermal conductive interlayer. ### Claim 8 (depends on 5) The semiconductor device as claimed in claim 5, wherein the circuit layer comprises a via portion extending through the lower dielectric layer and the electrical insulating and thermal conductive layer and a trench portion extending through the upper dielectric layer and communication with the via portion. ### Claim 9 (depends on 1) The semiconductor device as claimed in claim 1, further comprising an electrical and thermal conductive layer covering a surface of the circuit layer that is embedded in the dielectric structure, wherein a thermal conductivity of the electrical and thermal conductive layer is substantially greater than a thermal conductivity of the circuit layer. ### Claim 10 (depends on 9) The semiconductor device as claimed in claim 9, further comprising a seed layer, a barrier layer or a combination thereof covering a surface of the circuit layer that is embedded in the dielectric structure. ### Claim 11 (depends on 9) The semiconductor device as claimed in claim 9, further comprising an etch stop layer disposed between the semiconductor substrate and the dielectric structure and in contact with the electrical insulating and thermal conductive layer. ### Claim 12 A stacked semiconductor device, comprising: a first semiconductor device comprising: a first semiconductor substrate; a first surface dielectric layer disposed over the first semiconductor substrate; a first circuit layer embedded in the first surface dielectric layer; a first electrical and thermal conductive layer in physical contact with the first circuit layer, wherein a thermal conductivity of the first electrical and thermal conductive layer is substantially greater than a thermal conductivity of the first circuit layer; and a first electrical insulating and thermal conductive layer covering a first outer surface of the first surface dielectric layer, wherein a thermal conductivity of the first electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the first surface dielectric layer; and a second semiconductor device disposed over and bonded to the first semiconductor device, comprising: a second semiconductor substrate; a second surface dielectric layer disposed over the second semiconductor substrate; and a second electrical insulating and thermal conductive layer covering a second outer surface of the second surface dielectric layer and in physical contact with the first electrical insulating and thermal conductive layer. ### Claim 13 (depends on 12) The stacked semiconductor device as claimed in claim 12, wherein a material of each of the first electrical insulating and thermal conductive layer and the second electrical insulating and thermal conductive layer comprises boron nitride (h—BN) or aluminum nitride (AlN). ### Claim 14 (depends on 12) The stacked semiconductor device as claimed in claim 12, wherein the first semiconductor device further comprises a first circuit layer embedded in the first surface dielectric layer, and the second semiconductor device further comprises a second circuit layer embedded in the second surface dielectric layer and bonded with the first circuit layer. ### Claim 15 (depends on 14) The stacked semiconductor device as claimed in claim 14, wherein the first semiconductor device further comprises a first electrical and thermal conductive layer covering the first circuit layer, and a thermal conductivity of the first electrical and thermal conductive layer is substantially greater than a thermal conductivity of the first circuit layer. ### Claim 16 (depends on 14) The stacked semiconductor device as claimed in claim 14, wherein the second semiconductor device further comprises a second electrical and thermal conductive layer covering the second circuit layer, and a thermal conductivity of the second electrical and thermal conductive layer is substantially greater than a thermal conductivity of the circuit layer. ### Claim 17 A manufacturing method of a semiconductor device, comprising: forming an electrical insulating and thermal conductive layer over a semiconductor substrate; forming a dielectric structure over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure; forming a stepped opening in the dielectric structure, wherein the opening extending through the dielectric structure and the electrical insulating and thermal conductive layer; forming a circuit layer in the dielectric structure by a damascene process, wherein the circuit layer fills the stepped opening and comprises a bottom surface closest to the semiconductor substrate, and a lower surface of the electrical insulating and thermal conductive layer is substantially coplanar with the bottom surface of the circuit layer. ### Claim 18 (depends on 17) The manufacturing method of the semiconductor device as claimed in claim 17, wherein forming the dielectric structure further comprises: forming a lower dielectric layer over the electrical insulating and thermal conductive layer; forming an upper dielectric layer over lower dielectric layer, wherein the opening comprises a via opening extending through the lower dielectric layer and the electrical insulating and thermal conductive layer, and a trench opening extending through the upper dielectric layer and communication with the via opening. ### Claim 19 (depends on 17) The manufacturing method of the semiconductor device as claimed in claim 17, further comprising: forming an etch stop layer right prior to or right after the electrical insulating and thermal conductive layer is formed. ### Claim 20 (depends on 17) The manufacturing method of the semiconductor device as claimed in claim 17, further comprising: forming an electrical and thermal conductive layer over the dielectric structure before the circuit layer is formed, wherein a thermal conductivity of the electrical and thermal conductive layer is substantially greater than a thermal conductivity of the circuit layer.