# US 12,002,758 B2 · Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer

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- Number: US 12,002,758 B2
- Document ID: US12002758B2
- Status: Granted
- Kind: B2
- Application number: 17/453,516
- Filed: 2021-11-04
- Published: 2023-05-04
- Granted: 2024-06-04
- Earliest claimed: 2021-11-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ruilong Xie; Takeshi Nogami; Roy R. Yu; Balasubramanian Pranatharthiharan; Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US12002758B2

## CPC

- H10W 20/427: {Power or ground buses}
- H10D 1/692: {Electrodes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 72/00: Interconnections or connectors in packages
- H10W 20/0698: {Local interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

## Claims

### Claim 1

A method comprising:
forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer;
forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails;
depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench;
forming a first contact to a first metal layer of the plurality of layers, wherein forming the first contact comprises:
forming first recesses in a second metal layer of the plurality of layers; and
filling the first recesses with an insulative material; and
forming a second contact to the second metal layer, wherein forming the second contact comprises:
forming second recesses in the first metal layer; and
filling the second recesses with the insulative material.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming at least one backside conductive via that extends through the BILD layer or the semiconductor layer and contacts a first backside power rail of the backside power rails,
wherein the trench is proximate to the backside conductive via, and
wherein one of the first contact or the second contact couples with the backside conductive via.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the trench comprises:
applying a hard mask layer overlapping the backside conductive via and portions of the BILD layer or the semiconductor layer; and
etching through the BILD layer or the semiconductor layer and partly through the dielectric layer.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
performing chemical-mechanical polishing after depositing the plurality of layers to define a bottom surface of the BILD layer or the semiconductor layer, the backside MIM capacitor, and the backside conductive via;
forming an interlayer dielectric (ILD) layer contacting the bottom surface; and
etching through the ILD layer to expose the backside MIM capacitor.

### Claim 5 (depends on 1)

The method of claim 1,
wherein the first metal layer comprises a titanium nitride (TiN) metal,
wherein the second metal layer comprises a titanium carbide (TiC) metal, and
wherein a first insulation layer of the plurality of layers, arranged between the first metal layer and the second metal layer, comprises one or both of hafnium oxide and zirconium oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plurality of layers further comprises:
at least a second insulation layer; and
at least a third metal layer having a same metal as one of the first metal layer or the second metal layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein a longitudinal axis of the backside MIM capacitor is substantially parallel to the backside power rails.

### Claim 8

A semiconductor device comprising:
a backside interlayer dielectric (BILD) layer or a semiconductor layer;
a dielectric layer arranged above the BILD layer or the semiconductor layer;
backside power rails in the dielectric layer;
a backside metal-insulator-metal (MIM) trench capacitor extending through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, wherein the backside MIM trench capacitor comprises a first metal layer spaced apart from a second metal layer;
a first contact that overlaps a first region of the backside MIM trench capacitor, wherein in the first region, the first metal layer contacts the first contact, and the second metal layer is recessed and an insulative material contacts the first contact; and
a second contact that overlaps a second region of the backside MIM trench capacitor, wherein in the second region, the first metal layer is recessed and the insulative material contacts the second contact, and the second metal layer contacts the second contact.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
at least one backside conductive via that extends through the BILD layer or the semiconductor layer and contacts a first backside power rail of the backside power rails,
wherein one of the first contact or the second contact couples with the backside conductive via.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
an interlayer dielectric (ILD) layer contacting a bottom surface of the BILD layer or the semiconductor layer, the backside MIM trench capacitor, and the backside conductive via,
wherein the backside MIM trench capacitor is exposed through the ILD layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the bottom surface is defined by chemical-mechanical polishing.

### Claim 12 (depends on 8)

The semiconductor device of claim 8,
wherein the first metal layer comprises a titanium nitride (TiN) metal,
wherein the second metal layer comprises a titanium carbide (TiC) metal, and
wherein the first metal layer and the second metal layer are separated by a first insulation layer comprising one or both of hafnium oxide and zirconium oxide.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the backside MIM trench capacitor further comprises:
at least a second insulation layer; and
at least a third metal layer having a same metal as one of the first metal layer or the second metal layer.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein a longitudinal axis of the backside MIM trench capacitor is substantially parallel to the backside power rails.

### Claim 15

A computer program product for fabricating a semiconductor device, the computer program product comprising:
a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer;
forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails;
depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench;
forming a first contact to a first metal layer of the plurality of layers, wherein forming the first contact comprises:
forming first recesses in a second metal layer of the plurality of layers; and
filling the first recesses with an insulative material; and
forming a second contact to the second metal layer, wherein forming the second contact comprises:
forming second recesses in the first metal layer; and
filling the second recesses with the insulative material.

### Claim 16 (depends on 15)

The computer program product of claim 15, the operation further comprising:
forming at least one backside conductive via that extends through the BILD layer or the semiconductor layer and contacts a first backside power rail of the backside power rails,
wherein the trench is proximate to the backside conductive via, and
wherein one of the first contact or the second contact couples with the backside conductive via.

### Claim 17 (depends on 16)

The computer program product of claim 16, wherein forming the trench comprises:
applying a hard mask layer overlapping the backside conductive via and portions of the BILD layer or the semiconductor layer; and
etching through the BILD layer or the semiconductor layer and partly through the dielectric layer.

### Claim 18 (depends on 16)

The computer program product of claim 16, the operation further comprising:
performing chemical-mechanical polishing after depositing the plurality of layers to define a bottom surface of the BILD layer or the semiconductor layer, the backside MIM capacitor, and the backside conductive via;
forming an interlayer dielectric (ILD) layer contacting the bottom surface; and
etching through the ILD layer to expose the backside MIM capacitor.

### Claim 19 (depends on 15)

The computer program product of claim 15,
wherein the first metal layer comprises a titanium nitride (TiN) metal,
wherein the second metal layer comprises a titanium carbide (TiC) metal, and
wherein a first insulation layer of the plurality of layers, arranged between the first metal layer and the second metal layer, comprises one or both of hafnium oxide and zirconium oxide.

### Claim 20 (depends on 15)

The computer program product of claim 15, wherein the plurality of layers further comprises:
at least a second insulation layer; and
at least a third metal layer having a same metal as one of the first metal layer or the second metal layer.