# US 12,002,757 B2 · Staircase structure in three-dimensional memory device and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,757 B2 - Document ID: US12002757B2 - Status: Granted - Kind: B2 - Application number: 18/135,596 - Filed: 2023-04-17 - Published: 2023-08-10 - Granted: 2024-06-04 - Earliest claimed: 2020-06-05 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Di Wang; Wenxi Zhou; Zhiliang Xia; Zhong Zhang - Web page: https://patentgrep.com/patent/US12002757B2 ## CPC - H10P 50/283: {by chemical means} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)} - H10W 20/42: Vias, e.g. via plugs - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure. ## Claims ### Claim 1 A three-dimensional (3D) memory device, comprising: a memory array structure; and a staircase structure in an intermediate of the memory array structure and dividing the memory array structure into a first memory array structure and a second memory array structure each comprising a plurality of memory cells and located at one side of the staircase structure along a lateral direction, the staircase structure comprising a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure, wherein: a stair of the plurality of stairs comprises a conductor portion on a top surface of the stair and in contact with and connected to the bridge structure, and the conductor portion being connected to a first word line portion of the first memory array structure and a second word line portion at a same level with the first word line portion of the second memory array structure through the bridge structure. ### Claim 2 (depends on 1) The 3D memory device of claim 1, wherein the stair comprises a dielectric portion at a same level and in contact with the conductor portion, and the conductor portion comprises a first portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure in the lateral direction. ### Claim 3 (depends on 2) The 3D memory device of claim 2, wherein a dimension of the first portion of the conductor portion is less than a dimension of the conductor portion in a second lateral direction perpendicular to the lateral direction. ### Claim 4 (depends on 2) The 3D memory device of claim 2, wherein the conductor portion comprises a second portion overlapping with an immediately-lower stair. ### Claim 5 (depends on 4) The 3D memory device of claim 4, wherein the first portion and the second portion of the conductor portion each have a lateral shape of a right triangle. ### Claim 6 (depends on 4) The 3D memory device of claim 4, wherein the conductor portion comprises a third portion non-overlapping with a neighboring stair. ### Claim 7 (depends on 6) The 3D memory device of claim 6, wherein the third portion has a lateral shape of a right-angle trapezoid. ### Claim 8 (depends on 2) The 3D memory device of claim 2, wherein a length of the conductor portion is less than a length of the dielectric portion in a second lateral direction perpendicular to the lateral direction. ### Claim 9 (depends on 2) The 3D memory device of claim 2, wherein: the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicides, or polysilicon; and the dielectric portion comprises silicon nitride. ### Claim 10 (depends on 2) The 3D memory device of claim 2, wherein the stair further comprises a dielectric layer underlying and in contact with the conductor portion and the dielectric portion, the dielectric layer comprising silicon oxide. ### Claim 11 (depends on 2) The 3D memory device of claim 2, wherein: the bridge structure comprises a plurality of conductive layers, each of the conductive layers is in contact with the first word line portion and the second word line portion. ### Claim 12 A three-dimensional (3D) memory device, comprising: a memory array structure; and a staircase structure comprising a plurality of stairs extending along a first lateral direction, the plurality of stairs comprising a stair comprising a conductor portion on a top surface of the stair, the conductor portion being connected to the memory array structure, wherein: along a second lateral direction perpendicular to the first lateral direction, a width of the conductor portion near a bridge structure is larger than that far away from the bridge structure. ### Claim 13 (depends on 12) The 3D memory device of claim 12, wherein the staircase structure comprises a dielectric portion at a same level and in contact with the conductor portion, and the conductor portion comprises a first portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure. ### Claim 14 (depends on 13) The 3D memory device of claim 13, wherein the conductor portion comprises a second portion overlapping with an immediately-lower stair. ### Claim 15 (depends on 14) The 3D memory device of claim 14, wherein the first portion and the second portion of the conductor portion each have a lateral shape of a right triangle. ### Claim 16 (depends on 13) The 3D memory device of claim 13, wherein the conductor portion comprises a third portion non-overlapping with a neighboring stair. ### Claim 17 (depends on 13) The 3D memory device of claim 13, wherein: the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicides, or polysilicon; and the dielectric portion comprises silicon nitride. ### Claim 18 A three-dimensional (3D) memory device, comprising: a memory array structure; and a staircase structure in an intermediate of the memory array structure and dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction, the staircase structure comprising a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure, wherein: a stair of the plurality of stairs comprises a conductor portion on a top surface of the stair and in contact with and connected to the bridge structure, and the stair being connected to at least one of the first memory array structure and the second memory array structure through the bridge structure; and the conductor portion comprises a portion overlapping with an immediately-upper stair and in contact with the bridge structure. ### Claim 19 (depends on 18) The 3D memory device of claim 18, wherein the stair comprises a dielectric portion at a same level and in contact with the conductor portion and the bridge structure. ### Claim 20 (depends on 18) The 3D memory device of claim 18, wherein: the bridge structure comprises a plurality of conductive layers, and the conductor portion being connected to a first word line portion of the first memory array structure and a second word line portion at a same level as the first word line portion of the second memory array structure through one of the conductive layers.