# US 12,002,755 B2 · Metallization layer and fabrication method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,755 B2
- Document ID: US12002755B2
- Status: Granted
- Kind: B2
- Application number: 17/308,404
- Filed: 2021-05-05
- Published: 2022-07-28
- Granted: 2024-06-04
- Earliest claimed: 2021-01-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: I-Che Lee; Huai-Ying Huang; Ruei-Cheng Shiu
- Web page: https://patentgrep.com/patent/US12002755B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4421: {the principal metal being copper}
- H10W 90/00: Package configurations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening.

## Claims

### Claim 1

A method comprising:
receiving a substrate having a metal structure directly below a dielectric layer;
forming an opening in the dielectric layer to expose the metal structure
providing a gas that induces metal material from the metal structure to migrate into the opening; and
chemical mechanical polishing that planarizes an upper surface of the metal material within the opening, wherein the chemical mechanical polishing exposes a top electrode of a memory cell.

### Claim 2 (depends on 1)

The method of claim 1, wherein the metal material is copper.

### Claim 3 (depends on 1)

The method of claim 1, wherein the gas comprises a hydrogen compound and an oxygen compound or a compound that comprises hydrogen and oxygen.

### Claim 4 (depends on 1)

The method of claim 1, wherein the gas comprises water (H2O) or hydrogen (H2).

### Claim 5 (depends on 1)

The method of claim 1, further comprising annealing the metal material that has migrated into the opening.

### Claim 6

A method, comprising:
providing a substrate having a first region and a second region;
forming a first metallization layer over the substrate, wherein the first metallization layer comprises a wire;
forming an array of devices in the first region, wherein the devices include a top electrode;
depositing a dielectric layer in the second region, wherein the dielectric layer rises at least to a height of the top electrode;
forming a hole that goes through the dielectric layer, wherein the wire is exposed through the hole;
inducing metal from the wire to migrate into the hole so as to form a via in the hole, wherein inducing metal from the wire to migrate into the hole comprises alternately oxidizing and reducing the metal from the wire; and
planarizing, wherein planarizing makes upper surfaces of the via and the top electrode coplanar.

### Claim 7 (depends on 6)

The method of claim 6, wherein inducing the metal from the wire to migrate into the hole comprises exposing the metal to an oxygen-containing gas.

### Claim 8 (depends on 6)

The method of claim 6, wherein the devices comprise memory cells.

### Claim 9 (depends on 6)

The method of claim 6, wherein the devices comprise magnetic tunnel junctions.

### Claim 10 (depends on 6)

The method of claim 6, further comprising forming a second metallization layer, wherein the second metallization layer has contacts with the top electrode and with the via.

### Claim 11 (depends on 6)

The method of claim 6, further comprising annealing the via prior to planarizing.

### Claim 12

A method comprising:
providing a semiconductor substrate, wherein a wire comprising metal is disposed over the semiconductor substrate;
depositing a dielectric layer over the wire;
etching a hole through the dielectric layer, wherein the wire is exposed at a bottom of the hole;
exposing the wire to a gas, wherein the gas causes some of the metal in the wire to migrate upward into the hole by alternately oxidizing and reducing the metal, and the metal that migrates upward into the hole forms a metal structure in the hole.

### Claim 13 (depends on 12)

The method of claim 12, further comprising chemical mechanical polishing, wherein after chemical mechanical polishing, the metal structure provides a via that goes through the dielectric layer and is coupled to the wire.

### Claim 14 (depends on 12)

The method of claim 12, wherein the gas comprises a hydrogen compound and an oxygen compound and the wire comprises copper.

### Claim 15 (depends on 12)

The method of claim 12, further comprising annealing, wherein annealing reduces an oxygen concentration gradient in the metal structure.

### Claim 16 (depends on 12)

The method of claim 12, wherein the wire comprises copper and the dielectric layer is a low-k dielectric layer.

### Claim 17 (depends on 12)

The method of claim 12, wherein the dielectric layer comprises an etch stop layer and a low-k dielectric layer over the etch stop layer, and the metal structure extends above the etch stop layer.

### Claim 18 (depends on 12)

The method of claim 12, wherein alternately oxidizing and reducing the metal takes place at temperatures in the range from 50° C. to 200° C.

### Claim 19 (depends on 1)

The method of claim 1, wherein the gas oxidizes the metal material to form metal oxide molecules.

### Claim 20 (depends on 19)

The method of claim 19, wherein the gas reduces the metal oxide molecules.
