# US 12,002,750 B2 · Interconnect structure

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- Number: US 12,002,750 B2
- Document ID: US12002750B2
- Status: Granted
- Kind: B2
- Application number: 17/571,029
- Filed: 2022-01-07
- Published: 2022-04-28
- Granted: 2024-06-04
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsin-Yen Huang; Shao-Kuan Lee; Cheng-Chin Lee; Hai-Ching Chen; Shau-Lin Shue
- Web page: https://patentgrep.com/patent/US12002750B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.

## Claims

### Claim 1

An interconnect structure, comprising:
a first metal line and a second metal line surrounded by a first dielectric layer;
wherein the second metal line comprises a glue layer, a metal bulk layer over the glue layer and a metal capping layer over the metal bulk layer;
a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line;
a second dielectric layer over the dielectric block, the first metal line and the second metal line, wherein a bottom surface of the second dielectric layer is lower than a top surface of the dielectric block;
a first via surrounded by the second dielectric layer and electrically connected to the first metal line;
an encapsulating layer interposing between the first metal line and the first dielectric layer, wherein a top surface of the second metal line is substantially level to a top surface of the encapsulating layer; and
an etching stop layer along and in contact with the top surface of the second metal line and the top surface of the dielectric block, wherein a bottom surface of the etching stop layer is level to the top surface of the encapsulating layer and a top surface of the metal capping layer.

### Claim 2 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the glue layer, the metal bulk layer and the metal capping layer are in contact with the encapsulating layer.

### Claim 3 (depends on 1)

The interconnect structure as claimed in claim 1, further comprising:
a transistor over a substrate;
a contact plug over a source/drain feature of the transistor; and
a second via over the contact plug, wherein the first metal line is over and in contact with the second via.

### Claim 4 (depends on 1)

The interconnect structure as claimed in claim 1, wherein a portion of the second dielectric layer extends between the first via and the dielectric block.

### Claim 5 (depends on 1)

The interconnect structure as claimed in claim 1, wherein a sidewall and the top surface of the dielectric block are in contact with the first via.

### Claim 6 (depends on 1)

The interconnect structure as claimed in claim 1, wherein a width of the first via is greater than a width of the first metal line.

### Claim 7 (depends on 1)

The interconnect structure as claimed in claim 1, further comprising:
a catalyst layer between the dielectric block and the portion of the first dielectric layer.

### Claim 8

An interconnect structure, comprising:
a first metal line in a first dielectric layer;
a dielectric block over the first dielectric layer;
an etching stop layer over the dielectric block and the first metal line, wherein the etching stop layer includes a first horizontal portion along a top surface of the first metal line, a first vertical portion along a sidewall of the dielectric block, and a second horizontal portion along a top surface of the dielectric block, and a bottom surface of the first horizontal portion of the etching stop layer is lower than a bottom surface of the dielectric block;
a second dielectric layer covering the first horizontal portion and the second horizontal portion of the etching stop layer; and
a catalyst layer between the dielectric block and the first dielectric layer, wherein the bottom surface of the first horizontal portion of the etching stop layer is level to a bottom surface of the catalyst layer.

### Claim 9 (depends on 8)

The interconnect structure as claimed in claim 8, wherein a top surface of the second horizontal portion is higher than a top surface of the first horizontal portion.

### Claim 10 (depends on 8)

The interconnect structure as claimed in claim 8, further comprising:
a second metal line in the first dielectric layer; and
a via in the second dielectric layer and on the second metal line.

### Claim 11 (depends on 10)

The interconnect structure as claimed in claim 10, wherein a bottom surface of the via is lower than a top surface of the first metal line.

### Claim 12 (depends on 10)

The interconnect structure as claimed in claim 10, wherein the etching stop layer includes a third horizontal portion along a top surface of the second metal line and in contact with the via.

### Claim 13 (depends on 10)

The interconnect structure as claimed in claim 10, wherein a dielectric constant of the etching stop layer is greater than a dielectric constant of the dielectric block.

### Claim 14

An interconnect structure, comprising:
a first dielectric layer over a substrate;
a first metal line and a second metal line through the first dielectric layer;
a dielectric block over the first dielectric layer;
an etching stop layer along an upper surface and a sidewall of the dielectric block and an upper surface of the second metal line;
a second dielectric layer over the etching stop layer;
a via extending through the second dielectric layer, the etching stop layer, and the dielectric block to the first metal line; and
a blocking layer between the second metal line and the etching stop layer, wherein the blocking layer includes amphiphilic organic molecules.

### Claim 15 (depends on 14)

The interconnect structure as claimed in claim 14, further comprising:
a catalyst layer between the dielectric block and the first dielectric layer; and
an encapsulating layer between first metal line and the first dielectric layer.

### Claim 16 (depends on 14)

The interconnect structure as claimed in claim 14, wherein the via partially covers the dielectric block.

### Claim 17 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the encapsulating layer further interposes between the second metal line and the first dielectric layer, and a top surface of the first metal line is lower than the top surface of the encapsulating layer.

### Claim 18 (depends on 14)

The interconnect structure as claimed in claim 14, wherein the amphiphilic organic molecules include organic sulfur compound, organic phosphor compound, or organic silicon compound.

### Claim 19 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the encapsulating layer is in direct contact with a sidewall of the first via and a sidewall of the first metal line.

### Claim 20 (depends on 8)

The interconnect structure as claimed in claim 8, further comprising:
an encapsulating layer between the first metal line and the first dielectric layer, wherein a sidewall of the catalyst layer is aligned with a sidewall of the encapsulating layer.