# US 12,002,747 B2 · Integrated bridge for die-to-die interconnects > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,747 B2 - Document ID: US12002747B2 - Status: Granted - Kind: B2 - Application number: 17/680,489 - Filed: 2022-02-25 - Published: 2022-12-08 - Granted: 2024-06-04 - Earliest claimed: 2019-12-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Bok Eng Cheah; Jenny Shio Yin Ong; Seok Ling Lim; Kooi Chi Ooi; Jackson Chung Peng Kong - Web page: https://patentgrep.com/patent/US12002747B2 ## CPC - H10W 20/496: {Capacitor integral with wiring layers} - H01G 4/1272: {Semiconductive ceramic capacitors} - H10D 1/692: {Electrodes} - H10W 20/427: {Power or ground buses} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/00: Interconnections or connectors in packages - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die. ## Claims ### Claim 1 An apparatus, comprising: a semiconductor package substrate; first and second semiconductor dies on a first side of the semiconductor package substrate; and a bridge interconnect between the first side and a second side of the semiconductor package substrate, the second side opposite the first side, the bridge interconnect comprising: a first section coupling the first semiconductor die to the second semiconductor die; and a second section between the first semiconductor die and the second side, the second section comprising ground and power planes coupled to the first semiconductor die. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the ground and power planes are coupled to package connections on the second side. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising a passive component coupled to the ground and power planes. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the passive component is embedded in the bridge interconnect. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the passive component resides on an external surface of the semiconductor package substrate. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein: the ground plane is a first ground plane; the power plane is a first power plane; the first section comprises electrical signal routing and second ground and second power planes, the electrical signal routing is between the second ground and second power planes and couples the first semiconductor die to the second semiconductor dies; and the second ground and second power planes are coupled to the first ground and first power planes. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising a third semiconductor die on the first side of the semiconductor package substrate, and a third section of the bridge interconnect, wherein the first semiconductor die is between the second and third semiconductor dies, and the third section couples the first semiconductor die to the third semiconductor die. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein: the ground plane is a first ground plane; the power plane is a first power plane; the first section comprises first electrical signal routing and second ground and second power planes; the first electrical signal routing is between the second ground and second power planes and couples the first semiconductor die to the second semiconductor die; the second ground and second power planes are coupled to the first ground and first power planes; the third section comprises second electrical signal routing third ground and third power planes; the second electrical signal routing is between the third ground and third power planes and couples the first semiconductor die to the third semiconductor die; and the third ground and third power planes are coupled to the first ground and first power planes. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein: the ground plane is a first ground plane; the power plane is a first power plane; and the bridge interconnect further comprises a fourth section comprising second ground and second power planes that couple the second semiconductor die to the first ground and first power planes. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the fourth section is adjacent the first section. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the bridge interconnect comprises a lateral cross section at least partially spanning under the first semiconductor die and the second semiconductor die. ### Claim 12 An apparatus comprising: a package substrate; first and second dies on the package substrate; and a bridge component coupling the first and second dies, the bridge component comprising ground and power planes between and coupling the first die and package connections opposite the first die. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the bridge component is embedded between opposing first and second surfaces of the package substrate, the first and second dies are on the first surface, and the package connections are on the second surface. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second die is coupled to the first ground and first power planes by the second ground and second power planes. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second ground plane is coupled to the first ground plane, the second power plane is coupled to the first power plane, and the second ground and second power planes are between the first die and the bridge component. ### Claim 16 (depends on 12) The apparatus of claim 12, wherein the ground plane is a first ground plane, and the power plane is a first power plane, and further comprising second ground and second power planes, wherein the second ground plane is coupled to the first ground plane, the second power plane is coupled to the first power plane, and the second ground and second power planes are on or coupled to a surface of the bridge component opposite the first die. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the second ground and second power planes couple the first ground and first power planes to the package connections. ### Claim 18 (depends on 12) The apparatus of claim 12, further comprising a capacitor coupled to the first ground and power planes. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the capacitor is between the first die and the first ground and power planes. ### Claim 20 (depends on 12) The apparatus of claim 12, further comprising a third die on the package substrate, wherein the first die is between the second and third dies, and the bridge component couples the first and third dies.