# US 12,002,746 B2 · Chip package structure with metal-containing layer

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- Number: US 12,002,746 B2
- Document ID: US12002746B2
- Status: Granted
- Kind: B2
- Application number: 17/744,884
- Filed: 2022-05-16
- Published: 2022-08-25
- Granted: 2024-06-04
- Earliest claimed: 2019-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Huan Chen; Kuo-Ching Hsu; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US12002746B2

## CPC

- H10W 70/66: Conductive materials thereof
- H10W 70/685: comprising multiple insulating layers
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/692: Ceramics or glasses
- H10W 70/695: Organic materials
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.

## Claims

### Claim 1

A chip package structure, comprising:
a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer, wherein the first pad and the second pad are respectively over a first surface and a second surface of the substrate, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad;
a nickel-containing layer over the first pad;
a conductive protection layer over the nickel-containing layer, wherein the conductive protection layer comprises tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad;
a chip over the second surface of the substrate; and
a conductive bump between the second pad and the chip.

### Claim 2 (depends on 1)

The chip package structure as claimed in claim 1, further comprising:
a second wiring substrate, wherein the first wiring substrate is over the second wiring substrate, the second wiring substrate comprises a second substrate and a resilient contact structure mounted to the second substrate, and the resilient contact structure is in direct contact with the conductive protection layer.

### Claim 3 (depends on 2)

The chip package structure as claimed in claim 2, wherein the resilient contact structure is a resilient metal strip.

### Claim 4 (depends on 2)

The chip package structure as claimed in claim 2, wherein the resilient contact structure penetrates into the conductive protection layer.

### Claim 5 (depends on 4)

The chip package structure as claimed in claim 4, wherein a portion of the conductive protection layer is between the resilient contact structure and the nickel-containing layer.

### Claim 6 (depends on 2)

The chip package structure as claimed in claim 2, wherein a first portion of the resilient contact structure is in the recess, and a second portion of the resilient contact structure is outside of the recess.

### Claim 7 (depends on 1)

The chip package structure as claimed in claim 1, further comprising:
an intermetallic compound layer between the conductive protection layer and the nickel-containing layer, wherein the intermetallic compound layer comprises tin and nickel.

### Claim 8 (depends on 1)

The chip package structure as claimed in claim 1, wherein a first sidewall of the substrate is vertically aligned with a second sidewall of the insulating layer.

### Claim 9 (depends on 1)

The chip package structure as claimed in claim 1, wherein the insulating layer is thicker than the conductive protection layer.

### Claim 10 (depends on 1)

The chip package structure as claimed in claim 1, wherein opposite edges of the nickel-containing layer are in direct contact with the insulating layer.

### Claim 11

A chip package structure, comprising:
a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer, wherein the first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the insulating layer partially covers the first pad;
a conductive protection element covering the first pad, wherein a bottommost end of the conductive protection element is closer to the first pad than a bottommost surface of the insulating layer, and the conductive protection layer comprises tin;
a metal-containing layer between the first pad and the conductive protection element, wherein the conductive protection element and the metal-containing layer are made of different materials;
a chip bonded to the second pad; and
a second wiring substrate, wherein the first wiring substrate is over the second wiring substrate, the second wiring substrate comprises a second substrate and a resilient contact structure mounted to the second substrate, and the resilient contact structure is electrically connected to the conductive protection element.

### Claim 12 (depends on 11)

The chip package structure as claimed in claim 11, wherein a first sidewall of the conductive protection element is aligned with a second sidewall of the metal-containing layer.

### Claim 13 (depends on 11)

The chip package structure as claimed in claim 11, wherein a first sidewall of the first wiring substrate and a second sidewall of the insulating layer are vertically aligned with each other.

### Claim 14 (depends on 11)

The chip package structure as claimed in claim 11, wherein the resilient contact structure is closer to the first pad than the bottommost surface of the insulating layer.

### Claim 15 (depends on 11)

The chip package structure as claimed in claim 11, wherein the resilient contact structure extends into the insulating layer.

### Claim 16 (depends on 11)

The chip package structure as claimed in claim 11, wherein the resilient contact structure extends into the conductive protection element.

### Claim 17 (depends on 11)

The chip package structure as claimed in claim 11, wherein the resilient contact structure has a J-shape in a cross-sectional view of the second wiring substrate.

### Claim 18

A chip package structure, comprising:
a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer, wherein the first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the insulating layer partially covers the first pad;
a tin-containing protection element covering the first pad, wherein the tin-containing protection element is thinner than the insulating layer;
a metal-containing layer between the tin-containing protection element and the first pad;
a chip bonded to the second pad; and
a second wiring substrate, wherein the first wiring substrate is over the second wiring substrate, the second wiring substrate comprises a second substrate and a contact structure mounted to the second substrate, the contact structure is electrically connected to the tin-containing protection element, and the contact structure penetrates into the tin-containing protection element.

### Claim 19 (depends on 18)

The chip package structure as claimed in claim 18, wherein the tin-containing protection element is wider than the contact structure.

### Claim 20 (depends on 18)

The chip package structure as claimed in claim 18, wherein the contact structure is closer to the first pad than a bottommost surface of the insulating layer.