# US 12,002,745 B2 · High performance integrated RF passives using dual lithography process

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- Number: US 12,002,745 B2
- Document ID: US12002745B2
- Status: Granted
- Kind: B2
- Application number: 17/544,693
- Filed: 2021-12-07
- Published: 2022-03-31
- Granted: 2024-06-04
- Earliest claimed: 2021-12-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Adel A. Elsherbini; Mathew J. Manusharow; Krishna Bharath; William J. Lambert; Robert L. Sankman; Aleksandar Aleksov; Brandon M. Rawlings; Feras Eid; Javier Soto Gonzalez; Meizi Jiao; Suddhasattwa Nad; Telesphor Kamgaing
- Web page: https://patentgrep.com/patent/US12002745B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H01F 17/0006: {Printed inductances (printed coils for dynamo-electric machines H02K3/26; printed circuits H05K)}
- H01F 27/2804: {Printed windings}
- H01F 27/40: Structural association with built-in electric component, e.g. fuse
- H01F 41/041: {Printed circuit coils (apparatus or processes for manufacturing printed circuits in general H05K3/00)}
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H10D 1/00: Resistors, capacitors or inductors
- H10D 1/20: Inductors
- H10D 1/692: {Electrodes}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H01F 27/2809: {on stacked layers}
- H10W 44/241: {for passive devices or passive elements}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

## Claims

### Claim 1

A capacitor in an electrical package comprising:
a first dielectric layer;
a first capacitor plate over a top surface of the first dielectric layer and along a sidewall of the first dielectric layer;
a dielectric spacer over a surface of the first capacitor plate;
a second capacitor plate separated from the first capacitor plate by the dielectric spacer layer; and
a second dielectric layer laterally adjacent to the first capacitor plate, the dielectric spacer, and the second capacitor plate, wherein the second dielectric layer has an uppermost surface at a same level as an upper surface of the second capacitor plate.

### Claim 2 (depends on 1)

The capacitor of claim 1, wherein the first and second capacitor plates are in a single routing layer of the package.

### Claim 3 (depends on 2)

The capacitor of claim 2, wherein the dielectric spacer is less than 10 μm thick.

### Claim 4 (depends on 2)

The capacitor of claim 2, wherein the first and second capacitor plates include interdigitated square meander extensions.

### Claim 5 (depends on 4)

The capacitor plate of claim 4, wherein the extensions are in three-dimensions.