# US 12,002,742 B2 · Semiconductor package structure

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- Number: US 12,002,742 B2
- Document ID: US12002742B2
- Status: Granted
- Kind: B2
- Application number: 17/838,412
- Filed: 2022-06-13
- Published: 2022-09-29
- Granted: 2024-06-04
- Earliest claimed: 2017-03-14
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Tzu-Hung Lin; Yuan-Chin Liu
- Web page: https://patentgrep.com/patent/US12002742B2

## CPC

- H10W 70/68: Shapes or dispositions thereof
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/695: Organic materials
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/50: Bond wires
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)

## Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a substrate comprising:
a first substrate partition having a first wiring structure; and
a second substrate partition adjacent to the first substrate partition and having a second wiring structure,
wherein the first substrate partition and the second substrate partition are surrounded and separated by a first molding material;
a first semiconductor die disposed over the substrate and electrically coupled to the first wiring structure, wherein a bottom surface of the first semiconductor die is higher than a top surface of the first molding material; and
a second semiconductor die disposed over the substrate and electrically coupled to the second wiring structure.

### Claim 2 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the first substrate partition and the second substrate partition are homogenous.

### Claim 3 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the first substrate partition and the second substrate partition are heterogeneous.

### Claim 4 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the first semiconductor die and the second semiconductor die are surrounded and separated by a second molding material.

### Claim 5 (depends on 4)

The semiconductor package structure as claimed in claim 4, wherein surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the second molding material.

### Claim 6 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a third substrate partition adjacent to the first substrate partition and/or the second substrate partition, and the third substrate partition has a third wiring structure, wherein the first substrate partition, the second substrate partition and the third substrate partition are surrounded by the first molding material.

### Claim 7 (depends on 6)

The semiconductor package structure as claimed in claim 6, wherein the first substrate partition, the second substrate partition and the third substrate partition are separated by the first molding material.

### Claim 8 (depends on 6)

The semiconductor package structure as claimed in claim 6, wherein the first semiconductor die or the second semiconductor die is also electrically coupled to the third wiring structure.

### Claim 9 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a third semiconductor die disposed over the substrate and electrically coupled to the first wiring structure and/or the second wiring structure.

### Claim 10 (depends on 9)

The semiconductor package structure as claimed in claim 9, wherein the first semiconductor die, the second semiconductor die and the third semiconductor die are surrounded and separated by a second molding material.

### Claim 11 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising:
a plurality of conductive structures disposed between the substrate and the first semiconductor die and between the substrate and the second semiconductor die; and
a plurality of bump structures disposed below the substrate, wherein the first semiconductor die and the second semiconductor die are electrically coupled to the plurality of bump structures through the plurality of conductive structures, the first wiring structure and the second wiring structure, respectively.

### Claim 12 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a frame disposed over the first substrate partition and the second substrate partition, wherein the frame surrounds the first semiconductor die and the second semiconductor die.

### Claim 13 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a frame surrounding the first substrate partition and the second substrate partition, wherein the frame is surrounded by the first molding material.

### Claim 14

A semiconductor package structure, comprising:
a first substrate having a first wiring structure;
a second substrate having a second wiring structure, wherein the first substrate and the second substrate are arranged side-by-side, and the first substrate and the second substrate are surrounded and separated by a first molding material;
a first semiconductor die disposed over the first substrate and electrically coupled to the first wiring structure;
a second semiconductor die disposed over the second substrate and electrically coupled to the second wiring structure;
a plurality of first antenna structures disposed over the first substrate and electrically coupled to the first wiring structure; and
a plurality of second antenna structures disposed over the second substrate and electrically coupled to the second wiring structure.

### Claim 15 (depends on 14)

The semiconductor package structure as claimed in claim 14, further comprising a connector disposed over the second substrate and not disposed over the first substrate.