# US 12,002,737 B2 · Electronic package and method of fabricating the same

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- Number: US 12,002,737 B2
- Document ID: US12002737B2
- Status: Granted
- Kind: B2
- Application number: 16/568,990
- Filed: 2019-09-12
- Published: 2020-11-19
- Granted: 2024-06-04
- Earliest claimed: 2019-05-14
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Pin-Jing Su; Cheng-Kai Chang
- Web page: https://patentgrep.com/patent/US12002737B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 72/7448: {the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/073: {of die-attach connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/853: {On the same surface}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.

## Claims

### Claim 1

An electronic package, comprising:
an encapsulating layer;
at least one interposer board embedded into the encapsulating layer and having a plurality of through-silicon vias;
a plurality of conductive pillars disposed in the encapsulating layer and free from being formed in the at least one interposer board and any interposer board, wherein the plurality of conductive pillars are in direct contact with the encapsulating layer and are free from being in direct contact with the at least one interposer board and the plurality of through-silicon vias, wherein a surface of the encapsulating layer, a surface of the at least one interposer board, end surfaces of the plurality of through-silicon vias and end surfaces of the plurality of conductive pillars are horizontally coplanar; and
at least one semiconductor chip as an electronic component disposed on the encapsulating layer and electrically connected to the plurality of conductive pillars and the plurality of through-silicon vias by a plurality of conductive bumps, wherein the plurality of conductive bumps are in direct contact with the electronic component, the plurality of conductive pillars, and the plurality of through-silicon vias, and the electronic component is free from being embedded in the encapsulating layer.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein the plurality of through-silicon vias or an end surface of the plurality of conductive pillars are exposed from a surface of the encapsulating layer.

### Claim 3 (depends on 1)

The electronic package of claim 1, wherein an active component, a passive component or a combination thereof is disposed on the encapsulating layer.

### Claim 4 (depends on 1)

The electronic package of claim 1, further comprising a wiring structure electrically connecting the electronic component to the conductive pillars and the through-silicon vias.

### Claim 5 (depends on 1)

The electronic package of claim 1, further comprising a wiring structure disposed on the encapsulating layer and electrically connected to the plurality of conductive pillars and the plurality of through-silicon vias.

### Claim 6 (depends on 5)

The electronic package of claim 5, further comprising a plurality of conductive elements disposed on the wiring structure and electrically connected via the wiring structure to the plurality of conductive pillars and the plurality of through-silicon vias.

### Claim 7 (depends on 1)

The electronic package of claim 1, further comprising a plurality of conductive elements disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias.