# US 12,002,735 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,735 B2 - Document ID: US12002735B2 - Status: Granted - Kind: B2 - Application number: 17/469,698 - Filed: 2021-09-08 - Published: 2021-12-30 - Granted: 2024-06-04 - Earliest claimed: 2018-12-18 - Applicants: Tien-Chien Cheng - Inventors: Tien-Chien Cheng - Web page: https://patentgrep.com/patent/US12002735B2 ## CPC - H10W 40/47: by flowing liquids, e.g. forced water cooling - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/257: {having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh or porous structures (H10W40/254, H10W40/251 take precedence)} - H10W 40/735: {by melting or evaporation of solids} - H10W 72/07236: {Soldering or alloying} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 76/60: Seals - H10W 76/63: characterised by their shape or disposition, e.g. between cap and walls of a container - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/721: {of bump connectors} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package is disclosed for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip, a housing lid and thermal-conductive liquid. A chip is disposed on the substrate layer and electrically coupled to the substrate layer. The chip includes at least one through silicon via (TSV). The housing lid is disposed above both the substrate layer and the chip. Also, the housing lid is coupled to the substrate layer at its edge for forming an internal space that encompasses the chip. The thermal-conductive liquid is filled within the internal space. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate layer; a chip, disposed on the substrate layer and electrically coupled to the substrate layer, wherein the chip comprises at least one through silicon via (TSV); a housing lid, disposed above both the substrate layer and the chip, and coupled to the substrate layer at its edge for forming an internal space that encompasses the chip; and thermal-conductive liquid, filled within the internal space; wherein two of the at least one TSV are configured to form a pipe that embeds within the chip, and the two TSVs are substantially connected to each other. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the at least one TSV is configured to partially penetrate the chip. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the at least one TSV is configured to entirely penetrate the chip. ### Claim 4 (depends on 1) The semiconductor package of claim 1, further comprising: at least one microchannel, disposed between two of the at least one TSV on a surface of the chip. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the thermal-conductive liquid comprises Chlorofluorocarbons (CFC). ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the housing lid comprises a plurality of holes that penetrate the housing lid, and the plurality of holes are configured to allow the thermal conductive liquid to flow into or flow out of the internal space. ### Claim 7 (depends on 6) The semiconductor package of claim 6, further comprising: a plurality of plugs, which are configured to block the plurality of holes for sealing the thermal conductive liquid within the internal space. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the plurality of plugs comprise a plurality of screws, the plurality of holes comprise a plurality of lateral threads, and the plurality of screws are configured to detachably engage with the plurality of lateral threads for blocking the inlet hole. ### Claim 9 (depends on 6) The semiconductor package of claim 6, wherein the housing lid further comprises: at least one cycling pipe, configured to connect a pair of the plurality of holes at an external side of the semiconductor package. ### Claim 10 (depends on 1) The semiconductor package of claim 1, further comprising: an adhesive layer, disposed between the housing lid and the substrate layer, and configured to substantially contact both the housing lid and the substrate layer for adhering the housing lid with the substrate layer. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the substrate layer further comprises a plurality of solder bumps, which are disposed between the substrate layer and an external printed circuit board (PCB), such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein the substrate layer further comprises a plurality of solder bumps, which are sandwiched between the substrate layer and the chip, such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps. ### Claim 13 A semiconductor package, comprising: a substrate layer; a chip, disposed on the substrate layer and electrically coupled to the substrate layer, wherein the chip comprises at least one through silicon via (TSV); a housing lid, disposed above both the substrate layer and the chip, and coupled to the substrate layer at its edge for forming an internal space that encompasses the chip; thermal-conductive liquid, filled within the internal space; and at least one microchannel disposed between two of the at least one TSV on a surface of the chip. ### Claim 14 (depends on 13) The semiconductor package of claim 13, further comprising a metal mesh, disposed on the surface of the chip and within the internal space, wherein the metal mesh is made of copper. ### Claim 15 (depends on 13) The semiconductor package of claim 13, further comprising a metal mesh, disposed on the surface of the chip and within the internal space, wherein the metal mesh is made of stainless steel. ### Claim 16 (depends on 13) The semiconductor package of claim 13, wherein the housing lid comprises: at least two holes, configured to substantially penetrate the housing lid; and at least one cycling pipe, configured to connect a pair of the at least two holes at an external side of the semiconductor package. ### Claim 17 (depends on 13) The semiconductor package of claim 13, wherein the thermal-conductive liquid comprises Chlorofluorocarbons (CFC). ### Claim 18 (depends on 13) The semiconductor package of claim 13, further comprising: an adhesive layer, disposed between the housing lid and the substrate layer, and configured to substantially contact both the housing lid and the substrate layer for adhering the housing lid with the substrate layer. ### Claim 19 (depends on 13) The semiconductor package of claim 13, wherein the substrate layer further comprises a plurality of solder bumps, which are disposed between the substrate layer and an external printed circuit board (PCB), such that the substrate layer is electrically coupled to the external PCB via the plurality of solder bumps. ### Claim 20 (depends on 13) The semiconductor package of claim 13, wherein the substrate layer further comprises a plurality of solder bumps, which are sandwiched between the substrate layer and the chip, such that the chip is electrically coupled to the substrate layer via the plurality of solder bumps.