# US 12,002,726 B2 · Semiconductor package and method of manufacture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,726 B2 - Document ID: US12002726B2 - Status: Granted - Kind: B2 - Application number: 18/112,715 - Filed: 2023-02-22 - Published: 2023-06-22 - Granted: 2024-06-04 - Earliest claimed: 2020-09-07 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jinwoo Park; Jongho Lee; Yeongkwon Ko - Web page: https://patentgrep.com/patent/US12002726B2 ## CPC - H10W 74/014: {using batch processing} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/635: {Through-vias} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7416: {used during dicing or grinding} - H10W 70/685: comprising multiple insulating layers - H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07236: {Soldering or alloying} - H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/281: {Auxiliary members} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate. ## Claims ### Claim 1 A method of manufacture for a semiconductor package, the method comprising: arranging at least one semiconductor chip on an upper surface of an interposer; forming a molding member on side surfaces of the at least one semiconductor chip; using an adhesive to attach a carrier substrate to an upper surface of the molding member and an upper surface of the at least one semiconductor chip; using a first blade having a first blade-width to cut away selected portions of the carrier substrate and cut away portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are disposed above portions of the molding member; using a second blade having a second blade-width narrower than the first blade-width to cut through the interposer and at least partially into a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separates a package structure including a cut portion of the interposer and the at least one semiconductor chip, collectively supported by a cut portion of the carrier substrate; and bonding the package structure to an upper surface of a package substrate. ### Claim 2 (depends on 1) The method of claim 1, wherein arranging the at least one semiconductor chip on the upper surface of the interposer further comprises arranging a first stacked plurality of second semiconductor chips and a second stacked plurality of second semiconductor chips on the upper surface of the interposer. ### Claim 3 (depends on 2) The method of claim 2, wherein forming the molding member further comprises forming the molding member on side surfaces of the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips. ### Claim 4 (depends on 3) The method of claim 3, wherein attaching the carrier substrate further comprises attaching the carrier substrate to an upper surface of the first stacked plurality of second semiconductor chips and an upper surface of the second stacked plurality of second semiconductor chips. ### Claim 5 (depends on 4) The method of claim 4, wherein the selected portions of the carrier substrate are disposed above the portions of the molding member between the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips. ### Claim 6 (depends on 5) The method of claim 5, wherein the combination of the first cutting groove and the second cutting groove separates the package structure including the first stacked plurality of second semiconductor chips. ### Claim 7 (depends on 1) The method of claim 1, further comprising: using a third blade having a third blade-width narrower than the second blade-width to cut through a remaining portion of the lower surface of the molding member in the second cutting groove to form a third cutting groove, wherein a combination of the first cutting groove, the second cutting groove and the third cutting groove separates the package structure. ### Claim 8 A method of manufacture for a semiconductor package, the method comprising: forming a molding member on side surfaces of semiconductor chips; using an adhesive to attach a carrier substrate to an upper surface of the molding member and an upper surface of the semiconductor chips; using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of the semiconductor chips; using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate; and bonding the package structure to an upper surface of a package substrate. ### Claim 9 (depends on 8) The method of claim 8, wherein the carrier substrate is a glass substrate. ### Claim 10 (depends on 8) The method of claim 8, further comprising: detaching the cut portion of the carrier substrate from the semiconductor chip by irradiating the adhesive with a laser to weaken an adhesive strength of the adhesive. ### Claim 11 A method of manufacture for a semiconductor package, the method comprising: arranging a first semiconductor chip, a first stacked plurality of second semiconductor chips and a second stacked plurality of second semiconductor chips on an upper surface of an interposer; forming a molding member on side surfaces of the first semiconductor chip, the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips; using a first blade having a first blade-width to partially cut into an upper surface of the molding member to form a first cutting groove; using a second blade having a second blade-width narrower than the first blade-width to cut through the interposer and at least partially into a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separates a package structure including a cut portion of the interposer, the first semiconductor chip and the first stacked plurality of second semiconductor chips; and bonding the package structure to an upper surface of a package substrate. ### Claim 12 (depends on 11) The method of claim 11, further comprising using an adhesive to attach a carrier substrate to the upper surface of the molding member, an upper surface of the first semiconductor chip, an upper surface of the first stacked plurality of second semiconductor chips and an upper surface of the second stacked plurality of second semiconductor chips. ### Claim 13 (depends on 12) The method of claim 12, wherein the carrier substrate is a glass substrate. ### Claim 14 (depends on 12) The method of claim 12, further comprising using the first blade to cut away selected portions of the carrier substrate and cut away portions of the adhesive underlying the selected portions of the carrier substrate, wherein the selected portions of the carrier substrate are disposed above portions of the molding member. ### Claim 15 (depends on 11) The method of claim 11, further comprising: using a third blade having a third blade-width narrower than the second blade-width to cut through a remaining portion of the lower surface of the molding member in the second cutting groove to form a third cutting groove, wherein a combination of the first cutting groove, the second cutting groove and the third cutting groove separates the package structure. ### Claim 16 A method of manufacture for a semiconductor package, the method comprising: providing a first semiconductor chip, a first stacked plurality of second semiconductor chips and a second stacked plurality of second semiconductor chips; forming a molding member on side surfaces of the first semiconductor chip, the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips; using an adhesive to attach a carrier substrate to an upper surface of the molding member, an upper surface of the first semiconductor chip, an upper surface of the first stacked plurality of second semiconductor chips and an upper surface of the second stacked plurality of second semiconductor chips; using a first blade having a first blade-width to cut away selected portions of the carrier substrate and cut away portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips; using a second blade having a second blade-width narrower than the first blade-width to cut through an interposer and at least partially into a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including the first semiconductor chip and the first stacked plurality of second semiconductor chips, collectively supported by a cut portion of the carrier substrate; and bonding the package structure to an upper surface of a package substrate. ### Claim 17 (depends on 16) The method of claim 16, wherein providing the first semiconductor chip, the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips comprises arranging the first semiconductor chip, the first stacked plurality of second semiconductor chips and the second stacked plurality of second semiconductor chips on an upper surface of the interposer. ### Claim 18 (depends on 17) The method of claim 17, wherein the package structure further comprises a cut portion of the interposer. ### Claim 19 (depends on 16) The method of claim 16, wherein the carrier substrate is a glass substrate. ### Claim 20 (depends on 16) The method of claim 16, further comprising: using a third blade having a third blade-width narrower than the second blade-width to cut through a remaining portion of the lower surface of the molding member in the second cutting groove to form a third cutting groove, wherein a combination of the first cutting groove, the second cutting groove and the third cutting groove separates the package structure.