# US 12,002,716 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 12,002,716 B2
- Document ID: US12002716B2
- Status: Granted
- Kind: B2
- Application number: 18/120,902
- Filed: 2023-03-13
- Published: 2023-07-06
- Granted: 2024-06-04
- Earliest claimed: 2021-03-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shu-Wen Shen; Chen-Ping Chen
- Web page: https://patentgrep.com/patent/US12002716B2

## CPC

- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure;
forming an isolation insulating layer so that an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a sacrificial cladding layer over the exposed upper portion of the fin structure;
performing an etching operation to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed upper portion of the fin structure;
forming a first dielectric layer over the sacrificial cladding layer;
forming a second dielectric layer made of a different material than the first dielectric layer over the first dielectric layer;
recessing the second dielectric layer; and
forming a third dielectric layer made of a different material than the second dielectric layer on the recessed second dielectric layer, thereby forming a wall fin structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein during the etching operation, a protection layer, which is an oxide of a material of the sacrificial cladding layer, is formed over the sacrificial cladding layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the oxide is formed by treating a surface of the sacrificial cladding layer by one or more of SO2 or O2.

### Claim 4 (depends on 3)

The method of claim 3, wherein the treating comprises a plasma treatment.

### Claim 5 (depends on 2)

The method of claim 2, wherein the protection layer is formed after a portion of the sacrificial cladding layer is removed.

### Claim 6 (depends on 5)

The method of claim 5, wherein the protection layer is formed before the lateral portions of the sacrificial cladding layer disposed on the isolation insulating layer are fully removed.

### Claim 7 (depends on 1)

The method of claim 1, wherein the sacrificial cladding layer is made of SiGe.

### Claim 8 (depends on 7)

The method of claim 7, wherein the sacrificial cladding layer is amorphous or polycrystalline.

### Claim 9

A method of manufacturing a semiconductor device, comprising:
forming fin structures each including a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer;
forming an isolation insulating layer so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer;
forming a sacrificial cladding layer over the exposed hard mask layer and stacked layer;
performing an etching operation to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer, wherein during the etching operation, a protection layer is formed over the sacrificial cladding layer;
forming a wall fin structure between the fin structures;
removing the hard mask layer;
forming a sacrificial gate structure over the fin structures;
forming sidewall spacers on sidewalls of the sacrificial gate structure and sidewalls of a part of the wall fin structure;
forming a source/drain structure over the fin structures adjacent the sidewall spacers;
forming a dielectric layer over the source/drain structure;
removing the sacrificial gate structure;
removing the sacrificial cladding layer;
removing the first semiconductor layers; and
forming a metal gate structure around the second semiconductor layers.

### Claim 10 (depends on 9)

The method of claim 9, wherein the sacrificial cladding layer is made of SiGe.

### Claim 11 (depends on 9)

The method of claim 9, wherein the etching operation comprises:
a breakthrough etching operation;
a main etching operation after the breakthrough etching operation;
an atomic layer treatment for forming the protection layer after the main etching operation; and
a defooting etching operation after the atomic layer treatment.

### Claim 12 (depends on 11)

The method of claim 11, wherein the atomic layer treatment comprises a plasma treatment using an oxygen containing gas.

### Claim 13 (depends on 12)

The method of claim 12, wherein the atomic layer treatment is performed at a temperature in a range from 25° C. to 100° C.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
the main etching operation stops before the lateral portions of the sacrificial cladding layer disposed on the isolation insulating layer are fully removed, and
the defooting etching operation fully removes the lateral portions of the sacrificial cladding layer disposed on the isolation insulating layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein after the defooting etching operation, a difference between a first width between outer faces of the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer at an interface between the exposed hard mask layer and the exposed stacked layer and a second width between outer faces of the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer at an interface between the exposed stacked layer and the isolation insulating layer is in a range from 0.5 nm to 1.0 nm, where the second width is greater than the first width.

### Claim 16 (depends on 11)

The method of claim 11, wherein:
the sacrificial cladding layer is made of amorphous SiGe, and
the forming the sacrificial cladding layer comprises:
conformally forming a layer for the sacrificial cladding layer over the exposed hard mask layer and stacked layer and on the isolation insulating layer; and
removing a part of the layer on a top of the hard mask layer and on the isolation insulating layer.

### Claim 17 (depends on 11)

The method of claim 11, wherein:
the forming the source/drain structure comprises:
recessing source/drain regions of the fin structures;
laterally recessing ends of the first semiconductor layers; and
forming insulating inner spacers on recessed ends of the first semiconductor layers; and
forming one or more semiconductor epitaxial layers, and
during the recessing, at least a part of the sacrificial cladding layer is removed.

### Claim 18

A method of manufacturing a semiconductor device, comprising:
forming a fin structure;
forming an isolation insulating layer so that an upper portion of the fin structure is exposed from the isolation insulating layer;
forming a sacrificial cladding layer over the exposed upper portion of the fin structure;
partially etching lateral portions of the sacrificial cladding layer;
forming a protection layer over the sacrificial cladding layer; and
removing a further portion of the lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of a hard mask layer and the fin structure.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
the sacrificial cladding layer is made of amorphous or polycrystalline of SiGe, and
the protection layer is an oxide of SiGe.

### Claim 20 (depends on 18)

The method of claim 18, wherein a thickness of the protection layer is in a range from 1 nm to 5 nm.