# US 12,002,714 B2 · Semiconductor device and forming method thereof

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- Number: US 12,002,714 B2
- Document ID: US12002714B2
- Status: Granted
- Kind: B2
- Application number: 17/884,518
- Filed: 2022-08-09
- Published: 2022-12-01
- Granted: 2024-06-04
- Earliest claimed: 2020-09-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Yi Lee; Kuan-Yu Wang; Cheng-Lung Hung; Chi-On Chui
- Web page: https://patentgrep.com/patent/US12002714B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/364: {of IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, removing portions of the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a first titanium nitride layer wrapping around the nanosheets, wherein an atomic ratio of titanium to nitrogen of the first titanium nitride layer is less than 1, and forming a metal fill layer over the first titanium nitride layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers;
removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers;
forming a gate dielectric wrapping around the second semiconductor layers, the gate dielectric comprising two gate dielectric layers respectively in contact with different ones of the second semiconductor layers;
forming a metal nitride layer on the gate dielectric, wherein the metal nitride layer has a filling portion filling into a first one of the plurality of the spaces each between adjacent two of the second semiconductor layers, wherein the filling portion of the metal nitride layer is in contact with both of the gate dielectric layers of the gate dielectric; and
forming a fill metal layer on the metal nitride layer, wherein the fill metal layer is not in physical contact with the filling portion of the metal nitride layer filling into the first one of the plurality of the spaces.

### Claim 2 (depends on 1)

The method of claim 1, wherein the metal nitride layer is formed at a temperature lower than 450° C.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
prior to forming the fill metal layer, forming a glue layer over the metal nitride layer, wherein the glue layer comprises nitride.

### Claim 4 (depends on 3)

The method of claim 3, wherein the glue layer is a titanium nitride.

### Claim 5 (depends on 3)

The method of claim 3, wherein the glue layer is not in physical contact with the filling portion of the metal nitride layer filling into the first one of the plurality of the spaces.

### Claim 6 (depends on 3)

The method of claim 3, wherein the glue layer is formed at a temperature higher than 350° C.

### Claim 7 (depends on 3)

The method of claim 3, wherein the glue layer is in contact with the metal nitride layer and the fill metal layer.

### Claim 8

A method of manufacturing a semiconductor device, comprising:
forming a multilayer stack on a substrate, wherein the multilayer stack comprises alternately stacked first semiconductor layers and second semiconductor layers;
etching trenches in the multilayer stack and the substrate to form pedestals, the pedestals extending in a first direction;
forming a sacrificial pattern extending in a second direction crossing the first direction;
removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers;
forming source/drain regions on opposite sides of the second semiconductor layers, the source/drain regions partially connecting the second semiconductor layers; and
replacing the sacrificial pattern with a metal gate structure, wherein replacing the sacrificial pattern with the metal gate structure comprises:
forming a gate dielectric on the second semiconductor layers, wherein the gate dielectric comprises two gate dielectric layers respectively in contact with different ones of the second semiconductor layers; and
forming a first TiN layer by a deposition process using titanium organometallic precursor and N2 plasma to dissociate the titanium organometallic precursor during forming the first TiN layer, wherein the first TiN layer has a filling portion filling into a space between the different ones of the second semiconductor layers, the filling portion is in contact with both of the gate dielectric layers of the gate dielectric.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first TiN layer has a ratio of titanium to nitrogen greater than 0.6.

### Claim 10 (depends on 8)

The method of claim 8, wherein replacing the sacrificial pattern with the metal gate structure further comprises:
forming a second TiN layer over the first TiN layer, wherein the second TiN layer has a stoichiometry different from a stoichiometry of the first TiN layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second TiN layer has a titanium amount greater than a titanium amount of the first TiN layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the first TiN layer is formed at a first temperature, and the second TiN layer is formed at a second temperature different from the first temperature.

### Claim 13 (depends on 12)

The method of claim 12, wherein the second temperature is higher than the first temperature.

### Claim 14 (depends on 12)

The method of claim 12, wherein the first TiN layer and the second TiN layer have different thicknesses.

### Claim 15 (depends on 12)

The method of claim 12, wherein the first TiN layer has a thickness greater than a thickness of the second TiN layer.

### Claim 16 (depends on 8)

The method of claim 8, wherein the first TiN layer merges into a continuous structure during the deposition process.

### Claim 17

A method of forming a semiconductor device, comprising:
patterning a substrate to form a fin, the fin having first epitaxial layers and second epitaxial layers alternately arranged;
removing the first epitaxial layers in a region of the fin; and
forming a gate stack in the region where the first epitaxial layers resided, wherein forming the gate stack comprises:
forming a gate dielectric around the second epitaxial layers, wherein the gate dielectric comprises two gate dielectric layers respectively in contact with different ones of the second epitaxial layers;
repeating a plurality of deposition cycles to form a titanium nitride layer on the gate dielectric, wherein the titanium nitride layer has a filling portion filling into one of spaces each between adjacent two of the second epitaxial layers, the filling portion of the titanium nitride layer is in contact with both of the gate dielectric layers of the gate dielectric, and wherein each deposition cycles comprises:
providing a titanium-based precursor free from TiCl4; and
providing a nitrogen-based ammonia-free plasma to dissociate the titanium-based precursor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the plurality of deposition cycles is from about 10 to about 50.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the gate stack further comprises:
performing an atomic layer deposition process after repeating the plurality of deposition cycles, wherein the atomic layer deposition process is performed using titanium tetrachloride (TiCl4) and ammonia (NH3).

### Claim 20 (depends on 19)

The method of claim 19, wherein the atomic layer deposition process is performed without using N2.