# US 12,002,712 B2 · Phase control in contact formation

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- Number: US 12,002,712 B2
- Document ID: US12002712B2
- Status: Granted
- Kind: B2
- Application number: 17/809,922
- Filed: 2022-06-30
- Published: 2022-11-03
- Granted: 2024-06-04
- Earliest claimed: 2019-04-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chun-Hsien Huang; I-Li Chen; Pin-Wen Chen; Yuan-Chen Hsu; Wei-Jung Lin; Chih-Wei Chang; Ming-Hsing Tsai
- Web page: https://patentgrep.com/patent/US12002712B2

## CPC

- H10W 20/052: {by treatments not introducing additional elements therein}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 70/234: {the processing being the formation of vias or contact holes}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/064: {by modifying the conductivity of conductive parts, e.g. by alloying}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

## Claims

### Claim 1

A method comprising:
forming a first metallic feature;
forming a dielectric layer over the first metallic feature;
etching the dielectric layer to form an opening, wherein a top surface of the first metallic feature is exposed through the opening;
etching the first metallic feature to form an opening extension in the first metallic feature, wherein a portion of the opening extension is directly underlying a portion of the dielectric layer;
performing a first treatment on the top surface of the first metallic feature, wherein the first treatment is performed through the opening, and the first treatment is performed using a first process gas, wherein the first treatment comprises a plasma treatment or a thermal treatment, and wherein at a time the first treatment is started, a top surface of the dielectric layer is exposed;
after the first treatment, performing a second treatment, wherein the second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas; and
depositing a second metallic feature in the opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first treatment is performed using the first process gas comprising oxygen (O2), and the second treatment is performed using the second process gas comprising hydrogen (H2).

### Claim 3 (depends on 2)

The method of claim 2, wherein the first treatment comprises the plasma treatment.

### Claim 4 (depends on 1)

The method of claim 1, wherein the etching the first metallic feature is more isotropic than the etching the dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the depositing the second metallic feature comprises a bottom-up deposition of tungsten.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first treatment is performed using the first process gas comprising a silicon-containing process gas, a boron-containing process gas, a phosphorous-containing process gas, or combinations thereof.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first treatment results in a layer comprising silicon, boron, phosphorous, or combinations thereof, to be deposited.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first metallic feature comprises a source/drain contact plug.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first metal feature comprises a gate electrode, and the second metallic feature comprises a contact plug.

### Claim 10

A method comprising:
forming a first metallic feature, wherein the first metallic feature comprises a gate electrode or a source/drain contact plug of a transistor;
forming an etch stop layer over the first metal feature;
forming a dielectric layer over the etch stop layer;
etching the dielectric layer and the etch stop layer to form an opening, with the first metallic feature exposed to the opening, wherein the opening has a first width;
etching the first metallic feature to form an opening extension underlying and joined to the opening, wherein the opening extension has a second width greater than the first width;
oxidizing a surface layer of the first metallic feature to form a metal oxide layer at a surface of the first metallic feature, wherein at a time the surface layer starts to be oxidized, a top surface of the dielectric layer is exposed;
performing a reduction reaction to reduce the metal oxide layer back to an elemental metal; and
performing a bottom-up deposition process to deposit a tungsten plug in the opening.

### Claim 11 (depends on 10)

The method of claim 10, wherein the oxidizing is performed using oxygen (02) as a process gas.

### Claim 12 (depends on 10)

The method of claim 10, wherein the reduction reaction is performed using hydrogen (H2) as a process gas.

### Claim 13 (depends on 10)

The method of claim 10, wherein the oxidizing the surface layer is performed through plasma oxidation.

### Claim 14 (depends on 10)

The method of claim 10, wherein a portion of the tungsten plug in the opening extension is directly underly and forms a horizontal interface with a portion of the etch stop layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein the tungsten plug has an alpha phase.

### Claim 16

An integrated circuit device comprising:
a first metallic feature comprising a first portion and a second portion over the first portion, wherein the second portion comprises an element selected from the group consisting essentially of silicon, boron, phosphorus, arsenic, and combinations thereof, and the first portion is free from the element;
a dielectric layer over the first metallic feature; and
a second metallic feature over the first metallic feature and having a portion in the dielectric layer, wherein the second metallic feature comprises a third portion and a fourth portion over the third portion, with the third portion over and contacting the second portion to form an interface therebetween, and wherein the third portion comprises the element, and the fourth portion is free from the element.

### Claim 17 (depends on 16)

The integrated circuit device of claim 16 further comprising an element-rich region adjacent to an interface between sidewalls of the second metallic feature and the dielectric layer, wherein the element-rich region comprises the element, and the element-rich region comprises a sidewall surface portion of the second metallic feature and a sidewall surface portion of the dielectric layer.

### Claim 18 (depends on 16)

The integrated circuit device of claim 16, wherein the element comprises silicon.

### Claim 19 (depends on 16)

The integrated circuit device of claim 16, wherein the first metallic feature comprises a lower source/drain contact plug or a gate electrode of a transistor, and the second metallic feature comprises an upper source/drain contact plug or a gate contact plug of the transistor.

### Claim 20 (depends on 16)

The integrated circuit device of claim 16, wherein the second metallic feature comprises tungsten.