# US 12,002,710 B2 · Semiconductor structure and methods of forming the same

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- Number: US 12,002,710 B2
- Document ID: US12002710B2
- Status: Granted
- Kind: B2
- Application number: 16/924,200
- Filed: 2020-07-09
- Published: 2022-01-13
- Granted: 2024-06-04
- Earliest claimed: 2020-07-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Hsin Chan; Jiing-Feng Yang; Kuan-Wei Huang; Meng-Shu Lin; Yu-Yu Chen; Chia-Wei Wu; Chang-Wen Chen; Wei-Hao Lin; Ching-Yu Chang
- Web page: https://patentgrep.com/patent/US12002710B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a plurality of mandrel patterns over a dielectric layer;
forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer, wherein the first spacer comprises a first spacer portion and a second spacer portion in contact with the first spacer portion, and the second spacer comprises a third spacer portion and a fourth spacer portion in contact with the third spacer portion, wherein the first spacer portion and the third spacer portion are derived by patterning a same layer, and the second spacer portion and the fourth spacer portion are derived by patterning another same layer, and wherein a first distance between a bottom surface of the second spacer portion and a bottom surface of the first spacer portion is larger than a second distance between a bottom surface of the fourth spacer portion and a bottom surface of the third spacer portion;
removing the plurality of mandrel patterns;
patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and
forming conductive lines laterally aside the dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein patterning the dielectric layer comprises forming a first dielectric pattern defined by the first spacer and a second dielectric pattern defined by the second spacer.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the conductive lines comprises:
forming first conductive lines spaced apart by the first dielectric pattern therebetween; and
forming second conductive lines spaced apart by the second dielectric pattern therebetween,
wherein a first spacing between the first conductive lines is larger than a second spacing between the second conductive lines.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a hard mask structure between the dielectric layer and the plurality of mandrel patterns, wherein patterning the dielectric layer comprises:
patterning the hard mask structure to transfer patterns of the first spacer and the second spacer into the hard mask structure, thereby foi ming a patterned hard mask structure; and
transferring the patterns into the dielectric layer by etching the dielectric layer uncovered by the patterned hard mask structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the conductive lines comprises:
forming a conductive layer to cover the dielectric layer and the patterned hard mask structure; and
performing a planarization process to remove excess portion of the conductive layer and the patterned hard mask structure over a top surface of the dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the first spacer and the second spacer comprises:
forming a spacer material layer on the plurality of mandrel patterns, wherein the spacer material layer comprises a first part having a first thickness and a second part having a second thickness less than the first thickness; and
etching the spacer material layer to form the first spacer and the second spacer, wherein the first spacer is a remained portion of the first part of the spacer material layer, and the second spacer is a remained portion of the second part of the spacer material layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the spacer material layer comprises:
forming a spacer layer over the dielectric layer to cover the plurality of mandrel patterns; and
trimming a portion of the spacer layer to reduce a thickness of the portion of the spacer layer.

### Claim 8 (depends on 1)

The method of claim 1,
wherein a width of the first spacer portion is larger than a width of the third spacer portion, and a width of the second spacer portion is substantially equal to a width of the fourth spacer portion.

### Claim 9

A method of forming a semiconductor structure, comprising:
forming a dielectric layer over a semiconductor substrate;
forming a hard mask structure on the dielectric layer;
forming mandrel patterns on the hard mask structure;
forming a first spacer layer to cover the mandrel patterns within a first region and a second region, wherein the first spacer layer is made of a single material having a single-layer structure and a bottom surface of the first spacer layer is in physical contact with the hard mask structure;
performing a thinning step by covering up a first portion of the first spacer layer within the first region, and thinning an exposed portion of the first spacer layer within the second region, thereby forming a partially thinned first spacer layer having the single-layer structure, wherein after the thinning step, the first spacer layer comprises the first portion within the first region and a second portion within the second region thinner than the first portion, and wherein both of the first portion and the second portion are made of the single-layer structure and the first portion is joined with the second portion after the thinning step;
forming a second spacer layer on the partially thinned first spacer layer directly after the thinning step, wherein a bottom surface of the second spacer layer is physically separated from the hard mask structure;
etching back the second spacer layer and etching back the partially thinned first spacer layer to form a spacer mask on sidewalls of the mandrel patterns, wherein the spacer mask comprises a first spacer that comprises a first spacer portion formed from the first portion of the first spacer layer and a second spacer portion formed from the second spacer layer and disposed on the first spacer portion, and a second spacer that comprises a third spacer portion formed from the second portion of the first spacer layer and a fourth spacer portion formed from the second spacer layer and disposed on the third spacer portion, wherein the first spacer is wider than the second spacer, and a bottom surface of the second spacer portion and a bottom surface of the fourth spacer portion are located at different levels with a bottom surface of the first spacer portion and a bottom surface of the third spacer portion;
removing the mandrel patterns; and
patterning the hard mask structure and the dielectric layer to transfer a pattern of the spacer mask into the hard mask structure and the dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein thinning the portion of the first spacer layer comprises: forming a patterned mask to cover the first portion of the first spacer layer within the first region; and
etching the exposed portion of the first spacer layer using the patterned mask as an etching mask to form the first spacer layer having the first portion and the second portion.

### Claim 11 (depends on 9)

The method of claim 9, wherein the first spacer layer and the second spacer layer are respectively formed by a single deposition step, and the second spacer layer is formed with the same thickness as the first spacer layer prior to performing the thinning step.

### Claim 12 (depends on 9)

The method of claim 9, wherein a first distance between the bottom surface of the second spacer portion and the bottom surface of the first spacer portion is larger than a second distance between the bottom surface of the fourth spacer portion and the bottom surface of the third spacer portion.

### Claim 13 (depends on 9)

The method of claim 9, wherein after etching back the second spacer layer and etching back the partially thinned first spacer layer to form the spacer mask, the first spacer portion and the third spacer portion has a L-shaped structure.

### Claim 14

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming an etching stop layer;
forming a dielectric layer over the substrate and on the etching stop layer;
forming a spacer material layer over the substrate and on the dielectric layer, wherein the spacer material layer comprises a first part having a first thickness and a second part having a second thickness less than the first thickness;
etching the spacer material layer to form a plurality of first spacers and a plurality of second spacers, wherein the plurality of first spacers is a remained portion of the first part of the spacer material layer, and the plurality of second spacers is a remained portion of the second part of the spacer material layer, and wherein the plurality of first spacers comprises a first spacer portion and a second spacer portion disposed on the first spacer portion, and the plurality of second spacers comprises a third spacer portion and a fourth spacer portion disposed on the third spacer portion, and a thickness of the fourth spacer portion is greater than a thickness of the second spacer portion;
patterning the etching stop layer and the dielectric layer using the plurality of first spacers and the plurality of second spacers to form a patterned etching stop layer and a patterned dielectric layer, wherein the patterned dielectric layer is fonned to have a first dielectric portion and a second dielectric portion, and the patterned etching stop layer is underlying the patterned dielectric layer; and
forming a conductive layer laterally aside the patterned dielectric layer, and laterally aside the patterned etching stop layer, comprising:
forming first conductive lines spaced apart from each other by the first dielectric portion therebetween;
forming second conductive lines spaced apart from each other by the second dielectric portion therebetween,
wherein a first spacing between the first conductive lines is different from a second spacing between the second conductive lines.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first dielectric portion is formed to have a first width different from a second width of the second dielectric portion, and the first spacing and the second spacing are defined by the first width and the second width, respectively.

### Claim 16 (depends on 14)

The method of claim 14, wherein a capacitance between the first conductive lines is less than a capacitance between the second conductive lines.

### Claim 17 (depends on 14)

The method of claim 14, wherein the patterned etching stop layer comprises etching stop portions having different widths.

### Claim 18 (depends on 14)

The method of claim 14, wherein top surfaces of the plurality of first spacers are aligned with top surfaces of the plurality of second spacers.

### Claim 19 (depends on 14)

The method of claim 14, wherein the first conductive lines are formed to extend in a first direction, and are spaced apart from each other in a second direction perpendicular to the first direction, and the second conductive lines are formed to extend in the first direction, and are spaced apart from each other in the second direction perpendicular to the first direction.

### Claim 20 (depends on 14)

The method of claim 14, further comprising:
forming a first hard mask layer over the substrate and on the dielectric layer;
forming a second hard mask layer over the substrate and on the first hard mask layer;
forming a third hard mask layer over the substrate and on the second hard mask layer; and
forming a fourth hard mask layer over the substrate and on the third hard mask layer, wherein the spacer material layer is formed on the fourth hard mask layer.