# US 12,002,707 B2 · Semiconductor structure and manufacturing method thereof

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- Number: US 12,002,707 B2
- Document ID: US12002707B2
- Status: Granted
- Kind: B2
- Application number: 17/471,256
- Filed: 2021-09-10
- Published: 2022-02-10
- Granted: 2024-06-04
- Earliest claimed: 2020-08-06
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Bingyu Zhu; Hai-Han Hung; Jingwen Lu
- Web page: https://patentgrep.com/patent/US12002707B2

## CPC

- H10D 84/0151: {Manufacturing their isolation regions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method for the semiconductor structure comprises: providing a substrate, wherein the substrate comprises active regions and isolation regions each located between the adjacent active regions, and each of the active regions comprises corner regions adjacent to the isolation regions; performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions; and performing a removing process to remove the oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises active regions and isolation regions each located between adjacent active regions of the active regions, and each of the active regions comprises corner regions adjacent to the isolation regions;
performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions;
performing a removing process to remove an oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region;
performing a depositing process to each of the active regions to form a gate dielectric layer covering only a top surface of each of the active regions; and
forming an isolation part covering the side wall of each of the corner regions, wherein a material of the isolation part is different from a material of the gate dielectric layer,
wherein performing the removing process comprises: performing an etching process to the isolation regions to form trenches from which the side walls of the corner regions are exposed, wherein each of the trenches is configured to form an isolation structure.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein performing the removing process further comprises: performing a first cleaning process to the trenches after the etching process, wherein a cleaning liquid of the first cleaning process comes into contact with the side wall of each of the corner regions.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein each of the isolation structures has a recess, the side wall of each of the corner regions is exposed from the recess;
performing the removing process comprises: performing a second cleaning process to the top surface of each of the active regions after the doping process, wherein in the second cleaning process, a cleaning liquid of the second cleaning process comes into contact with the side wall of each of the corner regions.

### Claim 4 (depends on 3)

The method for manufacturing the semiconductor structure of claim 3, wherein the gate dielectric layer is formed after the second cleaning process, and
the side wall of each of the corner regions is exposed from the gate dielectric layer and the isolation structure before the isolation part is formed.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein the doping ions comprise nitrogen ions, and an implantation dose of the doping ions is 1e12 to 1e16 atoms/cm2.

### Claim 6 (depends on 1)

The method for manufacturing the semiconductor structure of claim 1, wherein performing the doping process to implant the doping ions into the corner regions comprises:
providing a shielding layer on the substrate, wherein each of the active regions further comprises a central region located between adjacent corner regions of the corner regions, the shielding layer covering a top surface of the central region, the shielding layer being configured to shield the implantation of the doping ions, and
performing an ion implantation to the substrate.

### Claim 7 (depends on 6)

The method for manufacturing the semiconductor structure of claim 6, wherein a scope of implantation energy of the ion implantation is 1 to 6 KV.

### Claim 8 (depends on 6)

The method for manufacturing the semiconductor structure of claim 6, wherein the shielding layer further covers each of the corner regions, and each of the isolation regions is exposed from the shielding layer; and the ion implantation is performed to the substrate at an implantation angle.

### Claim 9 (depends on 8)

The method for manufacturing the semiconductor structure of claim 8, wherein the implantation angle is 5 to 60 degrees.

### Claim 10 (depends on 5)

The method for manufacturing the semiconductor structure of claim 5, wherein performing the doping process to implant the doping ions into the corner regions comprises:
providing a shielding layer on the substrate, wherein each of the active regions further comprises a central region located between adjacent corner regions of the corner regions, the shielding layer covering a top surface of the central region, the shielding layer being configured to shield the implantation of the doping ions, and
performing an ion implantation to the substrate.

### Claim 11

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises active regions and isolation regions each located between adjacent active regions of the active regions, and each of the active regions comprises corner regions adjacent to the isolation regions;
performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions;
performing a removing process to remove an oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region;
performing a depositing process to each of the active regions to form a gate dielectric layer covering only a top surface of each of the active regions; and
forming an isolation part covering the side wall of each of the corner regions, wherein a material of the isolation part is different from a material of the gate dielectric layer,
wherein each of the isolation regions is provided with an isolation structure having a recess, the side wall of each of the corner regions is exposed from the recess;
performing the removing process comprises: performing a second cleaning process to the top surface of each of the active regions after the doping process, wherein in the second cleaning process, a cleaning liquid of the second cleaning process comes into contact with the side wall of each of the corner regions, and
wherein the gate dielectric layer is formed after the second cleaning process, and the side wall of each of the corner regions is exposed from the gate dielectric layer and the isolation structure before the isolation part is formed.

### Claim 12

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises active regions and isolation regions each located between adjacent active regions of the active regions, and each of the active regions comprises corner regions adjacent to the isolation regions;
performing a doping process to implant doping ions into the corner regions, wherein the doping ions are configured to slow down an oxidation rate of the corner regions;
performing a removing process to remove an oxidized portion of the substrate after the doping process, wherein during the removing process, a side wall of each of the corner regions is exposed from a structure in the isolation region;
performing a depositing process to each of the active regions to form a gate dielectric layer covering only a top surface of each of the active regions; and
forming an isolation part covering the side wall of each of the corner regions, wherein a material of the isolation part is different from a material of the gate dielectric layer,
wherein performing the doping process to implant the doping ions into the corner regions comprises:
providing a shielding layer on the substrate, wherein each of the active regions further comprises a central region located between adjacent corner regions of the corner regions, the shielding layer covering a top surface of the central region, the shielding layer being configured to shield the implantation of the doping ions, and
performing an ion implantation to the substrate.