# US 12,002,705 B2 · Methods and apparatus for forming backside power rails

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- Number: US 12,002,705 B2
- Document ID: US12002705B2
- Status: Granted
- Kind: B2
- Application number: 17/670,777
- Filed: 2022-02-14
- Published: 2023-08-17
- Granted: 2024-06-04
- Earliest claimed: 2022-02-14
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: He Ren; Houssam Lazkani; Raman Gaire; Mehul Naik; Kuan-Ting Liu
- Web page: https://patentgrep.com/patent/US12002705B2

## CPC

- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/20: of semiconductor materials
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/2926: {Crystal orientations}
- H10P 50/242: {of Group IV materials}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 90/124: {by processing the backside of the wafers}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

## Claims

### Claim 1

A method for forming a sacrificial fill material, comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and
epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

### Claim 2 (depends on 1)

The method of claim 1, wherein the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide.

### Claim 3 (depends on 2)

The method of claim 2, wherein the silicon or the silicon germanium contains a dopant of boron, phosphorous, carbon, oxygen, or antimony.

### Claim 4 (depends on 2)

The method of claim 2, wherein the sacrificial fill material is SiGe0.4.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.

### Claim 6 (depends on 5)

The method of claim 5, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

### Claim 7 (depends on 1)

The method of claim 1 performed in an integrated cluster tool without an air break or intermediate wet preclean process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the rate of the hydrogen chloride gas is approximately 70 sccm.

### Claim 9 (depends on 1)

The method of claim 1 performed in a process to form a backside power via for a transistor structure.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.

### Claim 11

A method of forming a backside power rail contact for a source/drain epitaxial (Epi) structure of a transistor, comprising:
forming an opening in a substrate;
depositing a conformal layer of oxide on the substrate and in the opening;
performing an etching process on the substrate and the opening, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the conformal layer of oxide from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening;
epitaxially growing a sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr;
forming a source/drain Epi structure on the sacrificial fill material;
forming a gate material on the source/drain Epi structure;
forming at least one interconnect signal lines above the gate material;
flipping the substrate to reveal a backside of the substrate;
removing material of the substrate to expose the sacrificial fill material;
selectively etching the sacrificial fill material to remove the sacrificial fill material; and
forming the backside power rail contact which is self-aligned to the source/drain Epi structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein the sacrificial fill material is silicon germanium (SiGe).

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

### Claim 15 (depends on 11)

The method of claim 11, wherein the conformal layer of oxide is an aluminum oxide material.

### Claim 16 (depends on 11)

The method of claim 11, wherein the rate of the hydrogen chloride gas is approximately 70 sccm.

### Claim 17

A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a bottom portion of the opening while preserving the oxide layer on sidewalls of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and
epitaxially growing the sacrificial fill material in the opening using a bottom-up fill process by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

### Claim 18 (depends on 17)

The non-transitory, computer readable medium of claim 17, the method further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material and wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

### Claim 19 (depends on 17)

The non-transitory, computer readable medium of claim 17, wherein the rate of the hydrogen chloride gas is approximately 70 sccm, wherein the method is performed in an integrated cluster tool without an air break or intermediate wet preclean process, or wherein the method is performed in a process to form a backside power via for a transistor structure.

### Claim 20 (depends on 17)

The non-transitory, computer readable medium of claim 17, the method further comprising:
forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.