# US 12,002,686 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 12,002,686 B2
- Document ID: US12002686B2
- Status: Granted
- Kind: B2
- Application number: 17/004,202
- Filed: 2020-08-27
- Published: 2021-07-29
- Granted: 2024-06-04
- Earliest claimed: 2020-01-27
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Satoshi Tsukiyama; Satoru Takaku; Yuki Sugo; Ayana Amano
- Web page: https://patentgrep.com/patent/US12002686B2

## CPC

- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 72/01515: {Forming coatings}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/075: {of bond wires}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/473: {containing a filler}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first resin layer provided above a first surface of the substrate, the first resin layer including a plurality of types of resins having different molecular weights and a filler;
a first semiconductor chip provided above the first resin layer and the first surface; and
a second resin layer provided in at least a part of a first region between the substrate and the first resin layer, the second resin layer directly contacting the first resin layer, the second resin layer including:
at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and
a filler having a lower concentration than the filler of the first resin layer,
a third resin layer covering the first resin layer, the second resin layer and the substrate,
wherein
the third resin layer directly contacting the first surface of the substrate,
the first semiconductor chip directly contacting the first resin layer,
the substrate includes a recess, and the second resin layer is disposed in a second region between the recess and the first resin layer,
the recess has a first metal film and a second metal film, and the first and second metals are physically separated in the recess,
a first part of the first metal film and a first part of the second metal film directly contacting a bottom surface of the recess,
a second part of the first metal film and a second part of the second metal film being embedded in a side wall of the recess.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second semiconductor chip disposed between the substrate and the first resin layer; and
a wire electrically connecting the substrate and the second semiconductor chip, wherein
the second resin layer is provided in a third region between the wire and at least one of the substrate, the first resin layer or the second semiconductor chip is below the wire.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the third region includes a gap formed by the wire and filled by the second resin layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein among the plurality of types of resins having different molecular weights, a ratio of a minimum value to a maximum value of the molecular weights is equal to or less than a predetermined value.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the predetermined value is 1/10 or less.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the predetermined value is between 1/100 and 1/1000.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein
the first resin layer includes at least one of acrylic rubber or polyimide, and at least one of an epoxy resin or a phenol resin, and
the second resin layer includes at least one of the epoxy resin or the phenol resin.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the filler comprises silica.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein a top surface of the second resin layer is lower than a top edge of the recess.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the second resin layer is convex in the recess.

### Claim 11

A semiconductor device, comprising:
a substrate including a recess;
a first resin layer provided above a first surface of the substrate, the first resin layer including a filler;
a first semiconductor chip provided above the first resin layer; and
a second resin layer provided in the recess, the second resin layer directly contacting the first resin layer, and the second resin layer includes a filler having a lower concentration than the filler of the first resin layer,
wherein the recess has a first metal film and a second metal film, and the first and second metal films are physically separated in the recess,
the second resin layer is disposed in a second region between the recess and the first resin layer,
a first part of the first metal film and a first part of the second metal film directly contacting a bottom surface of the recess,
a second part of the first metal film and a second part of the second metal film being embedded in a side wall of the recess.