# US 12,002,685 B2 · Method for packaging chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,685 B2 - Document ID: US12002685B2 - Status: Granted - Kind: B2 - Application number: 17/620,345 - Filed: 2019-12-06 - Published: 2022-11-17 - Granted: 2024-06-04 - Earliest claimed: 2019-06-17 - Assignees: Weifang Goertek Microelectronics Co., Ltd. - Applicants: Weifang Goertek Microelectronics Co., Ltd. - Inventors: Baoguan Yin; Fei She; Dewen Tian; Qinglin Song - Web page: https://patentgrep.com/patent/US12002685B2 ## CPC - H10W 70/023: {Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps} - H10W 70/68: Shapes or dispositions thereof - H10W 70/027: {Mechanical treatments, e.g. deforming, punching or cutting} - H10W 74/01: Manufacture or treatment - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/075: {of bond wires} - H10W 72/07507: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/931: {Shapes of bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed is a method for packaging a chip, comprising the following steps: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a chip, wherein the chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the chip and fixes it on the baseplate; removing the release base material so as to obtain a package structure for the chip. ## Claims ### Claim 1 A method for packaging a chip, comprising: providing a baseplate formed with an open slot thereon penetrating through opposite sides of the baseplate; providing a release base material, wherein the release base material is bonded to a first side of the baseplate and covers the open slot; providing a first chip, wherein the first chip is mounted on the release base material at the position of the open slot; packaging a second side of the baseplate facing away from the release base material so as to form a packaging layer which packages the first chip to be fixed on the baseplate; and removing the release base material to obtain a package structure for the first chip; wherein the providing the first chip further comprises mounting the first chip on the release base material in a manner in which pins thereon face the release base material, mounting a second chip on the first chip in a manner in which pins thereon face away from the release base material, wherein the pins of the second chip are conducted to the baseplate through respective leads; wherein the packaging the second side of the baseplate further comprises, packaging the first chip, the second chip and the leads of the second chip and fixing all on the baseplate; and the method further comprises after removing the release base material, conducting the pins of the first chip to the baseplate through leads, and packaging the first chip and its pins from the first side of the baseplate. ### Claim 2 (depends on 1) The method of claim 1 for packaging a chip, wherein a top surface of the first chip is flush with or lower than a top surface of the baseplate; and the method further comprises, after packaging the second side of the baseplate, thinning the packaging layer. ### Claim 3 (depends on 1) The method of claim 1 for packaging a chip, wherein the providing the first chip further comprises, mounting the first chip on the release base material in a manner in which pins thereon face the release base material; and the method further comprises, after the removing the release base material, performing re-distribution on the baseplate. ### Claim 4 (depends on 3) The method of claim 3 for packaging a chip, further comprising, after the performing re-distribution, performing cutting to obtain a plurality of separate packaging structures. ### Claim 5 (depends on 1) The method of claim 1 for packaging a chip, wherein the providing the first chip further comprises, conducting the first chip to the baseplate through respective leads; and wherein the packaging the second side of the baseplate further comprises, packaging the first chip and its leads and fixing both on the baseplate; and further comprising mounting the second chip on the packaging layer and conducting the second chip to the baseplate through respective leads; and packaging the second chip, to form another packaging layer for packaging the second chip on the baseplate. ### Claim 6 (depends on 1) The method of claim 1 for packaging a chip, further comprising a further packaging of the first chip and its leads from the second side of the baseplate through a dispensing process. ### Claim 7 (depends on 1) The method of claim 1 for packaging a chip, the first chip having a size, wherein the second chip has the size. ### Claim 8 (depends on 1) The method of claim 1 for packaging a chip, wherein the packaging the second side of the baseplate is selected from the group consisting of, an injection molding process and a film-on-wire process. ### Claim 9 (depends on 1) The method of claim 1 for packaging a chip, wherein the release base material is selected from the group consisting of an adhesive tape, a pyrolysis film, a photolysis film, and a baseplate containing a release layer.