# US 12,002,682 B2 · Tip-to-tip graphic preparation method

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- Number: US 12,002,682 B2
- Document ID: US12002682B2
- Status: Granted
- Kind: B2
- Application number: 17/783,641
- Filed: 2020-07-23
- Published: 2023-01-05
- Granted: 2024-06-04
- Earliest claimed: 2019-12-30
- Assignees: Shanghai Ic R&D Center Co., Ltd
- Applicants: Shanghai Ic R&D Center Co., Ltd
- Inventors: Yanli Li; Yushu Yang; Qiang Wu
- Web page: https://patentgrep.com/patent/US12002682B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 76/4088: {Processes for improving the resolution of the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention disclosures a Tip-to-Tip pattern preparation method, comprising: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, forming a first patterned photoresist layer which has a first Tip-to-Tip pattern by EUV lithography, and transferring the first Tip-to-Tip pattern to the second hard mask layer by etching; then forming a second patterned photoresist layer which has a second Tip-to-Tip pattern by the EUV lithography, and transferring the second Tip-to-Tip pattern to the second hard mask layer by etching; finally, transferring the first Tip-to-Tip pattern and the second Tip-to-Tip pattern to the layer to be etched. The above method needs only performing the EUV lithography twice to form the small-sized Tip-to-Tip pattern with a period halved, that is, the EUV lithography and etching are used for reducing lithography layers and realizing to form the small-sized Tip-to-Tip pattern with the period halved.

## Claims

### Claim 1

A Tip-to-Tip pattern preparation method, comprising:
step S1: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, performing EUV lithography on the first photoresist layer to form a first patterned photoresist layer, which has a first Tip-to-Tip pattern;
step S2: using the first patterned photoresist layer as a mask, sequentially etching the first dielectric layer and the sacrificial layer to the upper surface of the second hard mask layer, thus forming a patterned sacrificial layer which has the first Tip-to-Tip pattern;
step S3: forming a spacer layer on the sidewall of the patterned sacrificial layer to fill Tip-to-Tip spaces of the first Tip-to-Tip pattern and expose a part of the upper surface of the second hard mask layer in other area;
step S4: forming a patterned protective layer to mask areas exposed by the patterned sacrificial layer and the spacer layer and expose the upper surface of the patterned sacrificial layer, using the patterned protective layer as a mask to remove the patterned sacrificial layer and the second hard mask layer thereunder, thus exposing a part of the upper surface of the first hard mask layer;
step S5: removing the patterned protective layer and sequentially forming a second dielectric layer and a second photoresist layer above the first hard mask layer, the second hard mask layer, and the spacer layer, and performing the EUV lithography on the second photoresist layer to form a second patterned photoresist layer, which has a second Tip-to-Tip pattern, the second Tip-to-Tip pattern and the first Tip-to-Tip pattern are interlaced;
step S6: using the second patterned photoresist layer as a mask, sequentially etching the second dielectric layer, the spacer layer and the second hard mask layer to the upper surface of the first hard mask layer, thus transferring the second Tip-to-Tip pattern into the spacer layer and the second hard mask layer;
step S7: removing the second patterned photoresist layer and the second dielectric layer, using the spacer layer and the second hard mask layer as a mask and etching the first hard mask layer and the layer to be etched to the upper surface of the substrate, thus forming a Tip-to-Tip pattern composed of the first Tip-to-Tip pattern interlaced with the second Tip-to-Tip pattern in the layer to be etched.

### Claim 2 (depends on 1)

The Tip-to-Tip pattern preparation method of claim 1, wherein the first hard mask layer comprises a metal nitride layer or a metal conductive layer; the layer to be etched comprises a low-K dielectric layer and a TEOS layer thereon, the first hard mask layer is covered above the TEOS layer.

### Claim 3 (depends on 1)

The Tip-to-Tip pattern preparation method of claim 1, wherein in step S1, the first Tip-to-Tip pattern comprises multiple first Tip-to-Tip lines and trenches between the adjacent first Tip-to-Tip lines, each of the first Tip-to-Tip lines has a first Tip-to-Tip space, line width of each of the first Tip-to-Tip lines is 14 nm˜24 nm, line width of each of the trenches between the adjacent first Tip-to-Tip lines is 26 nm˜36 nm, and line width of each the first Tip-to-Tip space is 18 nm˜25 nm; in step S7, line width of each of Tip-to-Tip lines in the Tip-to-Tip pattern is 10 nm˜15 nm, line width of each of trenches between the adjacent Tip-to-Tip lines is 10 nm˜15 nm, and line width of a Tip-to-Tip space in each of the Tip-to-Tip lines is 20 nm˜25 nm.

### Claim 4 (depends on 3)

The Tip-to-Tip pattern preparation method of claim 3, wherein in step S1, the trenches in the first Tip-to-Tip pattern are periodic and corresponding periodic width thereof is 40 nm˜60 nm; in step S7, the trenches in the Tip-to-Tip pattern are periodic and corresponding periodic width thereof is 20 nm˜30 nm.

### Claim 5 (depends on 1)

The Tip-to-Tip pattern preparation method of claim 1, wherein in step S4, the formation process of the patterned protective layer comprises:
step S41: coating a protective layer on the upper surfaces of the patterned sacrificial layer, the spacer layer and the second hard mask layer, the upper surface of the protective layer is not lower than the upper surface of the patterned sacrificial layer;
step S42: removing the excess protective layer to form the patterned protective layer, the upper surface of the patterned protective layer is flush with the upper surface of the patterned sacrificial layer.

### Claim 6 (depends on 5)

The Tip-to-Tip pattern preparation method of claim 5, wherein the protective layer comprises an organic carbon layer.

### Claim 7 (depends on 1)

The Tip-to-Tip pattern preparation method of claim 1, wherein in step S3, the formation process of the spacer layer comprises:
step S31: coating a spacer material on the upper surfaces of the patterned sacrificial layer and the second hard mask layer;
step S32: retaining the spacer material on the side wall of the patterned sacrificial layer and in the first Tip-to-Tip spaces of the first Tip-to-Tip pattern, and removing the excess spacer material.

### Claim 8 (depends on 7)

The Tip-to-Tip pattern preparation method of claim 7, wherein the thickness of the spacer layer is 13 nm˜15 nm.

### Claim 9 (depends on 7)

The Tip-to-Tip pattern preparation method of claim 7, wherein in step S32, removing the excess spacer material by a dry etching process.

### Claim 10 (depends on 7)

The Tip-to-Tip pattern preparation method of claim 7, wherein the material of the spacer layer comprises TiOx, wherein x is any value between 1 and 2.