# US 12,002,681 B2 · High electron mobility transistor and fabricating method of the same

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- Number: US 12,002,681 B2
- Document ID: US12002681B2
- Status: Granted
- Kind: B2
- Application number: 17/515,541
- Filed: 2021-10-31
- Published: 2023-04-13
- Granted: 2024-06-04
- Earliest claimed: 2021-10-12
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Ming-Hua Chang; Kun-Yuan Liao; Lung-En Kuo; Chih-Tung Yeh
- Web page: https://patentgrep.com/patent/US12002681B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 50/246: {of Group III-V materials}
- H10P 50/267: {using plasmas}
- H10P 50/283: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

## Claims

### Claim 1

A fabricating method of a high electron mobility transistor, comprising:
providing a substrate;
forming a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a photoresist from bottom to top to cover the substrate;
patterning the photoresist to form a patterned photoresist;
performing a dry etching process to etch the hard mask material layer and the metal compound material layer to transform the hard mask material layer into a hard mask and the metal compound material layer into a metal compound layer by taking the patterned photoresist as a first mask, wherein a spacer surrounds the patterned photoresist, the hard mask and the metal compound layer, and the spacer is generated by by-products which are formed during the dry etching process; and
after the dry etching process, etching the P-type group III-V compound material layer by taking the spacer and the patterned photoresist as a second mask; and
removing the spacer, the patterned photoresist and the hard mask.

### Claim 2 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, further comprising:
after removing the spacer, the patterned photoresist and the hard mask, forming a source electrode, a drain electrode and a gate electrode on the substrate.

### Claim 3 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, wherein the etching gas used during the dry etching process comprises C4F8, SF6, CF4, CHxF4-x, BCl3 or Cl2, and X is a positive number which is smaller than 4.

### Claim 4 (depends on 3)

The fabricating method of a high electron mobility transistor of claim 3, wherein an operational power of the dry etching process is greater than 100 W, and an operational pressure of the dry etching process is greater than 50 mTorr.

### Claim 5 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, wherein the spacer comprises carbon, silicon, fluorine, titanium or chlorine.

### Claim 6 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, wherein while etching the P-type group III-V compound material layer, the active layer serves as an etching stop layer.

### Claim 7 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, wherein the channel layer comprises gallium nitride, gallium indium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride.

### Claim 8 (depends on 1)

The fabricating method of a high electron mobility transistor of claim 1, wherein the active layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride.

### Claim 9 (depends on 1)

The he fabricating method of a high electron mobility transistor of claim 1, wherein the P-type group III-V compound material layer comprises P-type gallium nitride.

### Claim 10 (depends on 1)

The he fabricating method of a high electron mobility transistor of claim 1, wherein the hard mask comprises silicon nitride and the metal compound layer comprises titanium nitride or tantalum nitride.