# US 12,002,680 B2 · Method of manufacturing a III-N enhancement mode HEMT device

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- Number: US 12,002,680 B2
- Document ID: US12002680B2
- Status: Granted
- Kind: B2
- Application number: 17/345,229
- Filed: 2021-06-11
- Published: 2022-06-09
- Granted: 2024-06-04
- Earliest claimed: 2020-12-08
- Assignees: Imec Vzw
- Applicants: Imec Vzw
- Inventors: Niels Posthuma; Stefaan Decoutere
- Web page: https://patentgrep.com/patent/US12002680B2

## CPC

- H10D 64/0124: {to Group III-V semiconductors}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/6738: {Schottky barrier electrodes}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/411: {for FETs}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10P 50/266: {by vapour etching only}
- H10P 50/667: {by liquid etching only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

## Claims

### Claim 1

A method comprising:
providing a semiconductor structure comprising:
a substrate;
a layer stack, wherein each layer of the layer stack comprises a Group III-nitride material; and
a p-type doped GaN layer on the layer stack;
providing, on the p-type doped GaN layer, a metal bi-layer, thereby forming a Schottky junction with the p-type doped GaN layer, the metal bi-layer comprising a first metal layer in contact with the p-type doped GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer; and
performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the p-type doped GaN layer parallel to the first cross section, wherein performing the patterning process comprises:
performing a first dry etching process using a first dry etch chemistry, thereby partially patterning the metal bi-laver, wherein a first etch rate of the first metal layer is less than a second etch rate of the second metal layer;
performing a second dry etching process using a second dry etch chemistry different from the first dry etch chemistry, thereby patterning the p-type doped GaN layer; and
performing a wet etching process upon the metal bi-layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first cross section is substantially the same at every position between the p-type doped GaN layer and a surface of the metal bi-layer opposite the p-type doped GaN layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a thickness of the second metal layer is within a range of 50 nm to 500 nm.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the first metal layer comprises TiN and the second metal layer comprises W.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the wet etching process is configured such that the first metal layer has a greater etch rate than the second metal layer so that the first periphery is aligned to the second periphery.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the wet etching process comprises subjecting, at a temperature in a range of 60° C.-95° C., the semiconductor structure to a chemistry comprising H2SO4 and H2O2.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the first dry etch chemistry comprises CHF3 and SF6.

### Claim 8 (depends on 1)

The method according to claim 1, wherein performing the second dry etching process comprises:
performing a third dry etching process using a third dry etch chemistry, thereby non-selectively etching the p-type doped GaN layer with respect to a layer beneath the p-type doped GaN layer, and
performing a fourth dry etching process using a fourth dry etch chemistry different from the third dry etch chemistry, thereby selectively etching the p-type doped GaN layer with respect to the layer beneath the p-type doped GaN layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the layer stack comprises:
a buffer layer overlying the substrate;
a channel layer on the buffer layer; and
a barrier layer on the channel layer, wherein a surface of the layer stack is comprised in the barrier layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein a thickness of the second metal layer is within a range of 80 nm to 120 nm.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the first metal layer comprises a third metal layer comprising TiN and a fourth metal layer comprising TaN.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the second metal layer comprises W.

### Claim 13 (depends on 11)

The semiconductor structure method according to claim 11, wherein the fourth metal layer contacts the p-type doped GaN layer.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the fourth metal layer has a thickness within a range of 1 nm to 2 nm.