# US 12,002,678 B2 · Gate spacing in integrated circuit structures

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- Number: US 12,002,678 B2
- Document ID: US12002678B2
- Status: Granted
- Kind: B2
- Application number: 17/033,228
- Filed: 2020-09-25
- Published: 2022-03-31
- Granted: 2024-06-04
- Earliest claimed: 2020-09-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Charles Henry Wallace; Mohit K. Haran; Paul A. Nyhus; Gurpreet Singh; Eungnak Han; David Nathan Shykind; Sean Michael Pursel
- Web page: https://patentgrep.com/patent/US12002678B2

## CPC

- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

## Claims

### Claim 1

An integrated circuit (IC) structure, comprising:
a first gate metal having a longitudinal axis;
a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal;
a first gate contact above the first gate metal;
a second gate contact above the second gate metal; and
an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

### Claim 2 (depends on 1)

The IC structure of claim 1, further comprising:
a dielectric material between the first gate contact and the second gate contact, wherein the dielectric material is in the unordered region.

### Claim 3 (depends on 1)

The IC structure of claim 1, further comprising:
a gate cut dielectric material between the first gate metal and the second gate metal.

### Claim 4 (depends on 3)

The IC structure of claim 3, wherein the gate cut dielectric material is at least partially coplanar with the unordered region.

### Claim 5 (depends on 3)

The IC structure of claim 3, wherein the gate cut dielectric material is in the unordered region.

### Claim 6 (depends on 1)

The IC structure of claim 1, wherein a distance between the first gate metal and the second gate metal is between 10 nanometers and 200 nanometers.

### Claim 7 (depends on 1)

The IC structure of claim 1, wherein the IC structure further includes:
an array of channel regions, including a first channel region and an adjacent second channel region, wherein axes of the first channel region and the second channel region are parallel and offset;
a first region proximate to the first channel region;
a second region proximate to the second channel region, wherein one of the first region and the second region is a source region of a transistor and another one of the first region and the second region is a drain region of the transistor; and
an insulating material region at least partially between the first region and the second region.

### Claim 8 (depends on 1)

The IC structure of claim 1, further comprising:
fin-shaped channel regions.

### Claim 9 (depends on 1)

The IC structure of claim 1, wherein the unordered region is under a guard ring of the IC structure.

### Claim 10 (depends on 9)

The IC structure of claim 9, wherein the first gate metal and the second gate metal are not under the guard ring.

### Claim 11 (depends on 1)

The IC structure of claim 1, wherein the unordered region is at a periphery of a memory array.

### Claim 12 (depends on 11)

The IC structure of claim 11, wherein the first gate metal and the second gate metal are not at the periphery of the memory array.

### Claim 13

An integrated circuit (IC) structure, comprising:
a first gate contact having a longitudinal axis;
a second gate contact, wherein the longitudinal axis of the first gate contact is aligned with a longitudinal axis of the second gate contact; and
a region having an unordered lamellar pattern, wherein the region is coplanar with the first gate contact and the second gate contact.

### Claim 14 (depends on 13)

The IC structure of claim 13, further comprising:
a dielectric material between the first gate contact and the second gate contact, wherein the dielectric material is in the region.

### Claim 15 (depends on 14)

The IC structure of claim 14, wherein the dielectric material includes nitrogen, oxygen, or carbon.

### Claim 16 (depends on 13)

The IC structure of claim 13, further comprising:
a gate cut dielectric material between the first gate contact and the second gate contact.

### Claim 17

An integrated circuit (IC) structure, comprising:
a first gate having a longitudinal axis;
a second gate, wherein the longitudinal axis of the first gate is aligned with a longitudinal axis of the second gate; and
a region having an unordered lamellar pattern, wherein the region is coplanar with or above the first gate and the second gate.

### Claim 18 (depends on 17)

The IC structure of claim 17, further comprising:
a dielectric material between the first gate and the second gate, wherein the dielectric material is in the region.

### Claim 19 (depends on 17)

The IC structure of claim 17, further comprising:
a gate cut dielectric material between the first gate and the second gate.

### Claim 20 (depends on 19)

The IC structure of claim 19, wherein the gate cut dielectric material is at least partially coplanar with the region.