# US 12,002,630 B2 · Ceramic electronic device and manufacturing method of the same

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- Number: US 12,002,630 B2
- Document ID: US12002630B2
- Status: Granted
- Kind: B2
- Application number: 17/939,851
- Filed: 2022-09-07
- Published: 2023-03-30
- Granted: 2024-06-04
- Earliest claimed: 2021-09-30
- Assignees: Taiyo Yuden Co., Ltd.
- Applicants: Taiyo Yuden Co., Ltd.
- Inventors: Kotaro Mizuno
- Web page: https://patentgrep.com/patent/US12002630B2

## CPC

- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- C04B 35/465: based on alkaline earth metal titanates
- C04B 35/4682: {based on BaTiO3 perovskite phase}
- C04B 35/47: based on strontium titanates
- C04B 35/486: Fine ceramics
- C04B 35/49: containing also titanium oxides or titanates
- C04B 35/64: Burning or sintering processes (C04B33/32 takes precedence {; powder metallurgy B22F})
- H01G 4/008: Selection of materials
- H01G 4/0085: {Fried electrodes}
- H01G 4/012: Form of non-self-supporting electrodes
- H01G 4/1227: {based on alkaline earth titanates}
- C04B 2235/3206: Magnesium oxides or oxide-forming salts thereof
- C04B 2235/3208: Calcium oxide or oxide-forming salts thereof, e.g. lime
- C04B 2235/3213: Strontium oxides or oxide-forming salts thereof
- C04B 2235/3418: Silicon oxide, silicic acids or oxide forming salts thereof, e.g. silica sol, fused silica, silica fume, cristobalite, quartz or flint
- C04B 2235/6025: Tape casting, e.g. with a doctor blade
- C04B 2235/6562: Heating rate
- C04B 2235/768: Perovskite structure ABO3
- C04B 2235/80: Phases present in the sintered or melt-cast ceramic products other than the main phase
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE

## Abstract

A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers including Ni as a main phase are alternately stacked. At least one of the plurality of dielectric layers includes a secondary phase including Si, at an interface between the at least one of the plurality of dielectric layers and one of the plurality of internal electrode layers next to the at least one of the plurality of dielectric layers. The one of the plurality of internal electrode layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In, at a region contacting the secondary phase at the interface.

## Claims

### Claim 1

A ceramic electronic device comprising:
a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers including Ni as a main phase are alternately stacked,
wherein at least one of the plurality of dielectric layers includes a secondary phase including Si, at an interface between the at least one of the plurality of dielectric layers and one of the plurality of internal electrode layers next to the at least one of the plurality of dielectric layers, and
wherein the one of the plurality of internal electrode layers includes a layer including an additive element including one or more of Au, Pt, Cu, Fe, Cr, Zn, and In, at a region contacting the secondary phase at the interface.

### Claim 2 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein a total amount of the additive element is 0.01 at % or more and 5 at % or less with respect to Ni, in the one of the plurality of internal electrode layers.

### Claim 3 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the layer is a single metal of the additive element, an alloy including the additive element, or an oxide of the additive element.

### Claim 4 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein a ratio of (a thickness of the secondary phase)/(a thickness of the layer) in a stacking direction of the plurality of dielectric layers and the plurality of internal electrode layers is 0.1 or more and 3 or less.

### Claim 5 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein each thickness of the plurality of dielectric layers is 0.5 μm or less.

### Claim 6 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein a peak of Si concentration appears in the secondary phase and a peak of the additive element concentration appears in the layer when STEM-EDS line analysis is performed in a stacking direction of the plurality of dielectric layers and the plurality of internal electrode layers.

### Claim 7 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein a thickness of the one of the plurality of internal electrode layers is 0.05 μm or more and 0.4 μm or less.

### Claim 8 (depends on 1)

The ceramic electronic device as claimed in claim 1, wherein the plurality of dielectric layers include barium titanate.

### Claim 9

A manufacturing method of a ceramic electronic device comprising:
forming a plurality of stack units by forming each of internal electrode patterns of a Ni paste on each of dielectric green sheets including sintering agent including SiO2, the Ni paste including an additive of one or more of Au, Pt, Cu, Fe, Cr, Zn and In;
forming a multilayer structure by stacking the plurality of stack units; and
firing the multilayer structure,
wherein a condition of the firing is adjusted so that at least one of dielectric layers formed from the dielectric green sheets includes a secondary phase including Si, at an interface between the at least one of dielectric layers and one of internal electrode layers formed from the internal electrode patterns next to the at least one of the dielectric layers, and a layer including the additive element is formed at a region of the one of internal electrode layers contacting the secondary phase.