# US 12,002,542 B2 · Write circuit of memory device and method of operating the same

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- Number: US 12,002,542 B2
- Document ID: US12002542B2
- Status: Granted
- Kind: B2
- Application number: 18/074,392
- Filed: 2022-12-02
- Published: 2023-04-06
- Granted: 2024-06-04
- Earliest claimed: 2020-11-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company Limited
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company Limited
- Inventors: Xiu-Li Yang; Kuan Cheng; He-Zhou Wan; Wei-Yang Jiang
- Web page: https://patentgrep.com/patent/US12002542B2

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/419: Read-write [R-W] circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.

## Claims

### Claim 1

A device, comprising:
a data latch configured to receive a first clock signal and a second clock signal, and generate a write signal according to a write data signal inputted to the data latch;
a first logic element configured to generate the second clock signal based on the first clock signal;
a second logic element configured to generate the first clock signal based on a third clock signal and a fourth clock signal that are different from each other; and
a plurality of memory banks configured to operate according to the write signal, the third clock signal and the fourth clock signal.

### Claim 2 (depends on 1)

The device of claim 1, further comprising:
a third logic element configured to provide a first global write signal associated with the third clock signal to one of the plurality of memory banks; and
a fourth logic element configured to provide a second global write signal associated with the fourth clock signal to another one of the plurality of memory banks.

### Claim 3 (depends on 2)

The device of claim 2, further comprising:
a fifth logic element configured to receive the write signal, and coupled in series with the third logic element at a first node;
a sixth logic element configured to receive the write signal, and coupled in series with the fourth logic element at a second node;
a first switch coupled to the first node and configured to be controlled by the third clock signal; and
a second switch coupled to the second node and configured to be controlled by the fourth clock signal.

### Claim 4 (depends on 1)

The device of claim 1, further comprising:
a third logic element configured to receive the write signal;
a fourth logic element configured to receive the write signal;
a first switch configured to adjust a voltage level of an output terminal of the third logic element according to the third clock signal; and
a second switch configured to adjust a voltage level of an output terminal of the fourth logic element according to the fourth clock signal.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a third logic element configured to receive the write signal;
a fourth logic element configured to receive the write signal;
a first switch configured to adjust a voltage level of a power terminal of the third logic element according to the third clock signal; and
a second switch configured to adjust a voltage level of a power terminal of the fourth logic element according to the fourth clock signal.

### Claim 6 (depends on 5)

The device of claim 5, further comprising:
an inverter configured to receive the write signal to generate an inverted write signal;
a fifth logic element configured to receive the inverted write signal; and
a sixth logic element configured to receive the inverted write signal;
wherein the first switch is further configured to adjust a voltage level of a power terminal of the fifth logic element according to the third clock signal; and
the second switch is further configured to adjust a voltage level of a power terminal of the sixth logic element according to the fourth clock signal.

### Claim 7 (depends on 6)

The device of claim 6, further comprising:
a third switch configured to adjust a voltage level of an output terminal of the fifth logic element according to the third clock signal; and
a fourth switch configured to adjust a voltage level of an output terminal of the sixth logic element according to the fourth clock signal.

### Claim 8

A method, comprising:
generating a first global write signal based on a first clock signal and a write data signal;
driving a first memory bank by the first global write signal;
generating a second global write signal based on a second clock signal and the write data signal;
driving a second memory bank by the second global write signal;
generating a third global write signal based on a third clock signal and the write data signal; and
driving a third memory bank by the third global write signal,
wherein the first clock signal, the second clock signal and the third clock signal are different from each other, and
the first memory bank, the second memory bank and the third memory bank are different from each other.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
fixing each of the second global write signal and the third global write signal at a ground level when the first global write signal is transmitted to the first memory bank; and
fixing each of the first global write signal and the third global write signal at the ground level when the second global write signal is transmitted to the second memory bank.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
fixing each of the second global write signal and the first global write signal at the ground level when the third global write signal is transmitted to the third memory bank.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
determining one of the first memory bank and the second memory bank for performing a write procedure;
when the write procedure is performed to the first memory bank, providing the first clock signal in oscillation to generate the first global write signal according to the write data signal; and
when the write procedure is performed to the second memory bank, providing the second clock signal in oscillation to generate the second global write signal according to the write data signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
when the write procedure is performed to the first memory bank, suspending the second clock signal from oscillating to maintain the second global write signal at a ground level; and
when the write procedure is performed to the second memory bank, suspending the first clock signal from oscillating to maintain the first global write signal at the ground level.

### Claim 13

A method, comprising:
generating a write signal according to a write data signal inputted to a data latch, a first clock signal and a second clock signal;
generating the second clock signal based on the first clock signal;
generating the first clock signal based on a third clock signal and a fourth clock signal; and
operating a plurality of memory banks according to the write signal, the third clock signal and the fourth clock signal,
wherein the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are different from each other.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
inputting each of the third clock signal and the fourth clock signal into a first logic element; and
outputting the first clock signal by the first logic element.

### Claim 15 (depends on 14)

The method of claim 14, wherein generating the second clock signal comprises:
inverting the first clock signal to generate the second clock signal.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
providing a first global word line signal by a second logic element coupled to a first node; and
adjusting the first node according to the write signal and the third clock signal.

### Claim 17 (depends on 16)

The method of claim 16, wherein adjusting the first node comprises:
receiving the write signal by a third logic element coupled to the first node; and
adjusting a power terminal of the third logic element according to the third clock signal.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
providing a second global word line signal by a third logic element coupled to a second node;
inverting the write signal to generate an inverted write signal; and
adjusting the second node according to the inverted write signal and the third clock signal,
wherein the first global word line signal and the second global word line signal are complementary to each other.

### Claim 19 (depends on 18)

The method of claim 18, wherein adjusting the second node comprises:
receiving the inverted write signal by a fourth logic element coupled to the second node; and
adjusting a power terminal of the fourth logic element according to the third clock signal.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
controlling, according to the third clock signal, a first switch coupled between a power terminal and the first node; and
controlling, according to the third clock signal, a second switch coupled between the power terminal and the second node.