# US 12,002,541 B2 · Read clock toggle at configurable PAM levels > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,541 B2 - Document ID: US12002541B2 - Status: Granted - Kind: B2 - Application number: 17/854,924 - Filed: 2022-06-30 - Published: 2023-06-08 - Granted: 2024-06-04 - Earliest claimed: 2021-12-08 - Assignees: Advanced Micro Devices, Inc.; ATI Technologies ULC - Applicants: Advanced Micro Devices, Inc.; ATI Technologies ULC - Inventors: Aaron John Nygren; Michael John Litt; Karthik Gopalakrishnan; Tsun Ho Liu - Web page: https://patentgrep.com/patent/US12002541B2 ## CPC - G11C 7/1066: {Output synchronization} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals} - G11C 7/1069: {I/O lines read out arrangements} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register. ## Claims ### Claim 1 A read clock circuit for selectively providing a read clock signal from a memory to a memory controller over a memory bus, comprising: a pulse-amplitude modulation multi-level (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values; a mode register; and a digital control circuit coupled to the input of the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, and wherein a length of the initial toggling state and a length of the final toggling state are based on values in the mode register. ### Claim 2 (depends on 1) The read clock circuit of claim 1, wherein the two selected levels are based on one or more values in the mode register. ### Claim 3 (depends on 1) The read clock circuit of claim 1, wherein the digital control circuit is operable to cause the PAM driver to provide at least one static state in the preamble before the initial toggling state. ### Claim 4 (depends on 1) The read clock circuit of claim 1, wherein the two selected levels in the final toggling state are those employed for the read clock signal during the read operation. ### Claim 5 (depends on 1) The read clock circuit of claim 1, wherein the two selected levels during the initial toggling state are different from those in the final toggling state. ### Claim 6 (depends on 1) The read clock circuit of claim 1, wherein the digital control circuit is configurable to include a second toggling state between the initial toggling state and the final toggling state, the second toggling state toggling at a rate between those of the initial toggling state and the final toggling state. ### Claim 7 A method for selectively providing a read clock signal from a memory to a memory controller over a memory bus, the method comprising: deactivating a pulse-amplitude modulation (PAM) driver, capable of driving at least three levels indicating respective digital values, for a read clock signal following a memory read; responsive to a new memory read, activating the PAM driver and providing a preamble signal for a read clock signal, the preamble signal including, in order, at least one static state, an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate; determining a length of at least the initial toggling state and the final toggling state based on values in mode register; and following the preamble, toggling the PAM driver at the second rate to provide the read clock signal. ### Claim 8 (depends on 7) The method of claim 7, wherein the two selected levels are based on one or more values in the mode register. ### Claim 9 (depends on 7) The method of claim 7, further comprising providing at least one static state in the preamble before the initial toggling state. ### Claim 10 (depends on 7) The method of claim 7, wherein the two selected levels in the final toggling state are those employed for the read clock signal during a read operation. ### Claim 11 (depends on 7) The method of claim 7, wherein the two selected levels during the initial toggling state are different from those in the final toggling state. ### Claim 12 (depends on 7) The method of claim 7, further comprising providing a second toggling state between the initial toggling state and the final toggling state, the second toggling state toggling at a rate between those of the initial toggling state and the final toggling state. ### Claim 13 (depends on 7) The method of claim 7, wherein the PAM driver is capable of driving four levels indicating respective two-bit digital values relative to a signaling supply voltage of 1.2 volts. ### Claim 14 (depends on 7) The method of claim 7, wherein a toggling rate of the read clock is based on a toggling rate of a write clock received at the memory from the memory controller. ### Claim 15 A data processing system comprising: at least one processor; a memory controller coupled to the processor over a memory bus; and a dynamic random-access memory (DRAM) coupled to the memory controller over a memory bus, the DRAM including read clock (strobe) circuit for selectively providing a read clock signal from a memory to the memory controller over the memory bus, comprising: a pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values; a mode register; and and a digital control circuit coupled to the input of the PAM driver, the digital control circuit operable to cause the PAM driver to selectively provide the read clock signal during a read operation, and to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including, an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, and wherein a length of the initial toggling state and a length of the final toggling state are based on values in the mode register. ### Claim 16 (depends on 15) The data processing system of claim 15, wherein the two selected levels are based on one or more values in the mode register. ### Claim 17 (depends on 15) The data processing system of claim 15, wherein the digital control circuit is operable to cause the PAM driver to provide at least one static state in the preamble signal before the initial toggling state. ### Claim 18 (depends on 15) The data processing system of claim 15, wherein the two selected levels in the final toggling state are those employed for the read clock signal during the read operation. ### Claim 19 (depends on 15) The data processing system of claim 15, wherein the two selected levels during the initial toggling state are different from those in the final toggling state. ### Claim 20 (depends on 15) The data processing system of claim 15, wherein the digital control circuit is configurable to include a second toggling state between the initial toggling state and the final toggling state, the second toggling state including toggling at a rate between those of the initial toggling state and the final toggling state.