# US 12,002,540 B2 · On-die termination of address and command signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,540 B2 - Document ID: US12002540B2 - Status: Granted - Kind: B2 - Application number: 18/214,466 - Filed: 2023-06-26 - Published: 2024-03-28 - Granted: 2024-06-04 - Earliest claimed: 2006-12-21 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Ian Shaeffer; Kyung Suk Oh - Web page: https://patentgrep.com/patent/US12002540B2 ## CPC - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/022: {in I/O circuitry} - G11C 29/025: {in signal lines} - G11C 29/028: {with adaption or trimming of parameters} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal. ## Claims ### Claim 1 A memory controller to control the operation of a memory device, the memory controller comprising: a command/address (CA) transmission circuit; the memory controller to: send, using the CA transmission circuit, command/address (CA) signals via a CA bus to respective inputs of the memory device and a chip select signal to a chip select input of the memory device; and send to the memory device: register values, for storage in a plurality of registers of the memory device, including a register value that selects from two or more impedance values of on-die termination (ODT) impedances to apply to each of the respective inputs of the memory device that receive the CA signals; wherein the register values include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals, and a register value that selectively enables application of a CS ODT impedance to the chip select input. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein the memory controller is configured to send to the memory device, for storage in a first register field of the plurality of registers in the memory device, a value for setting a nominal CA ODT impedance. ### Claim 3 (depends on 2) The memory controller of claim 2, wherein the memory controller is configured to send to the memory device, for storage in a second register field of the plurality of registers in the memory device, a value for setting an alternative CA ODT impedance. ### Claim 4 (depends on 3) The memory controller of claim 3, wherein the memory controller is configured to send to the memory device, for storage in a third register field of the plurality of registers in the memory device, a value for determining specifying how the alternative CA ODT impedance, for termination of one or more CA signal inputs of the memory device that receive one or more of the CA signals from the memory controller, is enabled. ### Claim 5 (depends on 1) The memory controller of claim 1, wherein the memory controller is configured to send to the memory device, for storage in a respective register of the plurality of registers in the memory device, the value for selectively enabling application of the CS ODT impedance to the chip select input of the memory device. ### Claim 6 (depends on 5) The memory controller of claim 5, wherein the CS ODT impedance is different from a CA ODT impedance specified by a register value sent by the memory controller for storage in a respective register of the plurality of registers of the memory device. ### Claim 7 (depends on 1) The memory controller of claim 1, wherein the memory controller dynamically controls termination, at the memory device, of individual signal lines of the CA bus over which the command/address (CA) signals are sent to the memory device. ### Claim 8 (depends on 1) The memory controller of claim 1, further including a driver to drive a chip select (CS) signal onto the CA bus, wherein the plurality of registers of the memory device include: a first register comprising a plurality of register fields, wherein: a first register field is configured to store a value for enabling application of one of a plurality of CA on-die termination (ODT) impedance values to first inputs of the memory device that receive the CA signals; a second register field is configured to store a value for enabling application of one of a plurality of CS ODT impedance values to a second input of the memory device that receives the CS signal; and a third register field is configured to store a value for enabling application of a CK ODT impedance value to third inputs of the memory device that receive a CK signal. ### Claim 9 (depends on 8) The memory controller of claim 8, wherein the CA ODT impedance values are different from the CS ODT impedance values. ### Claim 10 (depends on 8) The memory controller of claim 8, wherein the plurality of registers of the memory device include: a second register comprising a plurality of register fields configured to store values for selecting one of the plurality of CA ODT impedance values for application to the first inputs of the memory device that receive the CA signals. ### Claim 11 (depends on 10) The memory controller of claim 10, wherein the plurality of registers of the memory device include: a third register configured to store values for selecting one of the plurality of CS ODT impedance values for application to the second input of the memory device that receives the CS signal. ### Claim 12 (depends on 10) The memory controller of claim 10, wherein the plurality of register fields in the second register include a first register field to store a first value for setting a nominal termination impedance for the first inputs that receive the CA signals, and a second register field to store a second value for setting an alternative termination impedance for the first inputs that receive the CA signals. ### Claim 13 (depends on 12) The memory controller of claim 12, wherein the plurality of register fields in the second register include a third register field to store a third value for specifying how the alternative termination impedance for the first inputs that receive the CA signals is enabled. ### Claim 14 (depends on 1) The memory controller of claim 1, wherein the memory controller is configured to send to the memory device a CAODT control signal that enables or disables on-die termination of at least a subset of signal lines of the CA bus. ### Claim 15 A method of operation of a memory controller for controlling a memory device, the method comprising: sending, from the memory controller, command/address (CA) signals to respective inputs of the memory device; and sending, from the memory controller to the memory device: register values, for storage in a plurality of registers of the memory device, wherein the register values represent two or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals; wherein the register values sent by the memory controller for storage in the plurality of registers of the memory device include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals. ### Claim 16 (depends on 15) The method of claim 15, including sending from the memory controller to the memory device, for storage in a first register field of the plurality of registers in the memory device, a value for setting a nominal CA ODT impedance. ### Claim 17 (depends on 16) The method of claim 16, including sending from the memory controller to the memory device, for storage in a second register field of the plurality of registers in the memory device, a value for setting an alternative CA ODT impedance. ### Claim 18 (depends on 17) The method of claim 17, including sending from the memory controller to the memory device, for storage in a third register field of the plurality of registers in the memory device, a value for determining specifying how the alternative CA ODT impedance, for termination of one or more CA signal inputs of the memory device that receive one or more of the CA signals from the memory controller, is enabled. ### Claim 19 (depends on 15) The method of claim 15, including sending from the memory controller to the memory device, for storage in a respective register in the memory device, a value for selecting one of a plurality of chip select (CS) ODT impedances for application to an input of the memory device that receives a CS signal. ### Claim 20 A memory controller to control the operation of a memory device, the memory controller comprising: a circuit to drive command and address signals; and a first circuit to drive a chip select (CS) signal; the memory controller is configured to: send, using the circuit to drive command and address signals, command/address (CA) signals to respective inputs of the memory device and, using the first circuit, the CS signal to a chip select input of the memory device; and send to the memory device: register values, for storage in a plurality of registers in the memory device, wherein the register values include: values representing two or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals; and a value for enabling application of one of a plurality of CS ODT impedance values to the chip select input of the memory device; wherein the register values sent by the memory controller for storage in the plurality of registers in the memory device include one or more register values to selectively enable application of the ODT impedances to the respective inputs that receive the CA signals.