# US 12,002,534 B2 · Memory array word line routing

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,534 B2
- Document ID: US12002534B2
- Status: Granted
- Kind: B2
- Application number: 17/842,256
- Filed: 2022-06-16
- Published: 2022-09-29
- Granted: 2024-06-04
- Earliest claimed: 2020-06-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Han Lin; Chenchen Jacob Wang; Yi-Ching Liu; Han-Jong Chia; Sai-Hooi Yeong; Yu-Ming Lin; Yih Wang
- Web page: https://patentgrep.com/patent/US12002534B2

## CPC

- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 8/14: Word line organisation; Word line lay-out
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 51/10: characterised by the top-view layout
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 51/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/80: characterised by the materials
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

## Claims

### Claim 1

A method comprising:
depositing a ferroelectric (FE) material on a first word line;
depositing an oxide semiconductor (OS) layer on the FE material;
patterning a first trench in the OS layer;
depositing a dielectric material in the first trench and on the FE material;
depositing an inter-metal dielectric (IMD) on the first word line;
patterning the IMD to form a second trench exposing the first word line;
patterning the dielectric material and the FE material to form a third trench;
forming a first contact in the second trench;
forming a second contact in the third trench; and
forming a first conductive line electrically coupling the first contact to the second contact.

### Claim 2 (depends on 1)

The method of claim 1, wherein the third trench is patterned to a depth greater than the second trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein the IMD, the dielectric material, and the FE material are patterned simultaneously to form the second trench and the third trench.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first word line is on an interconnect structure wherein the second contact is electrically coupled to the interconnect structure.

### Claim 5 (depends on 1)

The method of claim 1, wherein the third trench is patterned through the IMD.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first contact and the second contact are formed simultaneously.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a patterned photoresist on the IMD, wherein the second trench and the third trench are patterned through the patterned photoresist.

### Claim 8

A method comprising:
patterning a conductive layer in a multi-layer stack to form a word line and a first trench adjacent the word line;
depositing a ferroelectric (FE) material in the first trench;
depositing an oxide semiconductor (OS) layer in the first trench and on the FE material;
patterning the OS layer to form a second trench exposing the FE material;
forming a dielectric material in the second trench;
patterning the dielectric material and the FE material to form a third trench;
forming a first contact in the third trench; and
forming a first conductive line electrically coupled to the first contact and the word line.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming the multi-layer stack on a first interconnect structure, wherein the first contact is electrically coupled to the first interconnect structure.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
forming an inter-metal dielectric on the word line;
patterning the inter-metal dielectric to form a fourth trench exposing the word line; and
forming a second contact in the fourth trench, wherein the second contact electrically couples the word line to the first conductive line.

### Claim 11 (depends on 10)

The method of claim 10, wherein the third trench is patterned through the inter-metal dielectric.

### Claim 12 (depends on 8)

The method of claim 8, further comprising patterning the multi-layer stack to form a first staircase structure adjacent a first end of the word line and a second staircase structure adjacent a second end of the word line, wherein the first staircase structure and the second staircase structure are asymmetric in a cross-sectional view.

### Claim 13 (depends on 8)

The method of claim 8, further comprising forming an inter-metal dielectric on the word line, wherein the third trench is patterned through the inter-metal dielectric.

### Claim 14 (depends on 13)

The method of claim 13, further comprising planarizing the first contact, the inter-metal dielectric, and the multi-layer stack.

### Claim 15

A method comprising:
forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating conductive layers and dielectric layers;
patterning a first trench extending through the multi-layer stack;
depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench;
depositing an oxide semiconductor (OS) layer over the FE material;
depositing a dielectric material over the FE material;
forming an inter-metal dielectric (IMD) over the multi-layer stack;
forming a first conductive contact extending through the IMD to a first conductive layer of the multi-layer stack, wherein the first conductive contact is electrically coupled to the first conductive layer;
forming a second conductive contact extending through the dielectric material and the FE material; and
forming a conductive line electrically coupling the second conductive contact with the first conductive contact.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first conductive contact comprises forming a second trench extending through the IMD, wherein the second trench exposes a top surface of the first conductive layer, wherein forming the second conductive contact comprises forming a third trench extending through the dielectric material and the FE material, and wherein the second trench and the third trench are formed simultaneously.

### Claim 17 (depends on 15)

The method of claim 15, further comprising patterning the multi-layer stack such that the conductive layers and the dielectric layers have a staircase shape in a cross-sectional view.

### Claim 18 (depends on 17)

The method of claim 17, further comprising patterning the dielectric material to have the staircase shape in the cross-sectional view, wherein the IMD is formed over the multi-layer stack and the dielectric material after patterning the dielectric material and the multi-layer stack to have the staircase shape.

### Claim 19 (depends on 15)

The method of claim 15, wherein the dielectric material is formed extending through the IMD.

### Claim 20 (depends on 15)

The method of claim 15, wherein the first conductive contact and the second conductive contact are formed by separate processes.