Embedded memory transparent in-system built-in self-test

An integrated circuit (IC) device, comprising:

• a memory system comprising multiple memory cells;
• control circuitry configured to preclude functional circuitry from accessing the memory cells during test sessions;
• one or more registers;
• and
• memory built-in self-test (MBIST) circuitry configured to test subsets of the memory cells during the test sessions, including to store contents of the subsets of the memory cells in the one or more registers prior to testing the respective subsets of the memory cells, and restore the contents of the subsets of the memory cells from the one or more registers subsequent to testing the respective subsets of the memory cells;
• wherein the MBIST circuitry is further configured to,
• test a first set of m blocks of memory cells during a first test interval of a first one of the test sessions, and
• test a second set of m blocks of memory cells during a second test interval of the first test session,
• wherein each block includes one or more memory cells, and
• wherein m is a positive integer;
• wherein m>1;
• wherein the first and second sets of m blocks of memory cells overlap one another;
• and
• wherein the MBIST circuitry is further configured to,
• copy contents of the first set of m blocks of memory cells to registers prior to testing the first set of m blocks of memory cells,
• restore contents of a non-overlapping portion of the first set of m blocks of memory cells after testing the first set of m blocks of memory cells, and
• copy contents of a non-overlapping portion of the second set of m blocks of memory cells to the registers prior to testing the second set of m blocks of memory cells while retaining an overlapping portion of the first set of m blocks of memory cells in the registers.