# US 12,002,529 B2 · Shift register, semiconductor device, display device, and electronic device

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- Number: US 12,002,529 B2
- Document ID: US12002529B2
- Status: Granted
- Kind: B2
- Application number: 18/205,000
- Filed: 2023-06-02
- Published: 2023-10-05
- Granted: 2024-06-04
- Earliest claimed: 2005-10-18
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Atsushi Umezaki
- Web page: https://patentgrep.com/patent/US12002529B2

## CPC

- G11C 19/184: {with field-effect transistors, e.g. MOS-FET}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2320/02: Improving the quality of display appearance
- G09G 2320/043: Preventing or counteracting the effects of ageing
- G09G 2330/021: Power management, e.g. power saving
- G09G 2330/023: using energy recovery or conservation
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

## Claims

### Claim 1

A display device comprising:
a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a pixel comprising an eighth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the gate signal line,
wherein the other of the source and the drain of the second transistor is electrically connected to a first power source line,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a second power source line,
wherein a gate of the third transistor is electrically connected to a first wiring to which a start pulse is input,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third power source line,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the third power source line,
wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring,
wherein a gate of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the third power source line,
wherein a gate of the seventh transistor is electrically connected to the gate of the first transistor, and
wherein a gate of the eighth transistor is electrically connected to the gate signal line.

### Claim 2 (depends on 1)

The display device according to claim 1,
wherein the second transistor is configured to control a timing of supplying a potential of the first power source line to the gate of the eighth transistor through the second transistor, and
wherein the fourth transistor is configured to control a timing of supplying a potential of the third power source line to the gate of the first transistor through the fourth transistor.

### Claim 3

A display device comprising:
a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and
a pixel comprising an eighth transistor,
wherein one of a source and a drain of the first transistor is directly connected to a gate signal line,
wherein the other of the source and the drain of the first transistor is directly connected to a clock signal line,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor is directly connected to the gate signal line,
wherein the other of the source and the drain of the second transistor is directly connected to a first power source line,
wherein a gate of the second transistor is directly connected to a gate of the fourth transistor,
wherein the other of the source and the drain of the third transistor is directly connected to a second power source line,
wherein a gate of the third transistor is directly connected to a first wiring to which a start pulse is input,
wherein one of a source and a drain of the fourth transistor is directly connected to the gate of the first transistor,
wherein the other of the source and the drain of the fourth transistor is directly connected to a third power source line,
wherein one of a source and a drain of the fifth transistor is directly connected to the gate of the first transistor,
wherein the other of the source and the drain of the fifth transistor is directly connected to the third power source line,
wherein a gate of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the sixth transistor is directly connected to a second wiring,
wherein a gate of the sixth transistor is directly connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the seventh transistor is directly connected to the third power source line,
wherein a gate of the seventh transistor is directly connected to the gate of the first transistor, and
wherein a gate of the eighth transistor is directly connected to the gate signal line.

### Claim 4 (depends on 3)

The display device according to claim 3,
wherein the second transistor is configured to control a timing of supplying a potential of the first power source line to the gate of the eighth transistor through the second transistor, and
wherein the fourth transistor is configured to control a timing of supplying a potential of the third power source line to the gate of the first transistor through the fourth transistor.