# US 12,002,527 B2 · Programmable resistance memory on wide-bandgap semiconductor technologies > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,527 B2 - Document ID: US12002527B2 - Status: Granted - Kind: B2 - Application number: 17/584,297 - Filed: 2022-01-25 - Published: 2022-07-28 - Granted: 2024-06-04 - Earliest claimed: 2021-01-26 - Assignees: Attopsemi Technology Co., LTD - Applicants: Attopsemi Technology Co., LTD - Inventors: Shine C. Chung - Web page: https://patentgrep.com/patent/US12002527B2 ## CPC - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 11/1659: {Cell access} - G11C 11/1675: {Writing or programming circuits or methods} - G11C 13/0009: {RRAM elements whose operation depends upon chemical change} - G11C 13/003: {Cell access} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 17/16: using electrically-fusible links - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - H10B 61/10: {comprising components having two electrodes, e.g. diodes or MIM elements} - H10B 63/10: Phase change RAM [PCRAM, PRAM] devices - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - G11C 2213/72: Array wherein the access device being a diode - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Programmable resistive memory can be integrated with wide-bandgap semiconductor devices on a wide-bandgap semiconductor, silicon, or insulator substrate. The wide-bandgap semiconductor can be group IV-IV, III-V, or II-VI crystal or compound semiconductor, such as silicon carbide or gallium nitride. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a metal, silicon, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. The selector in a programmable resistive memory can be a MOS or diode fabricated by wide-bandgap semiconductor. ## Claims ### Claim 1 A programmable resistive memory integrated with wide-bandgap semiconductor devices, comprising: a plurality of programmable resistive cells, at least one of the cells comprising: a programmable resistive element (PRE) having one end coupled to a first supply voltage line; a selector having an active region divided into at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a semiconductor material on a semiconductor or insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line; and a gate fabricated on the layer of the semiconductor material with a sandwich of dielectric in between, the gate coupled to a third supply voltage line, the gate configured to divide the active region into the first active region and the second active region, wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state, wherein the semiconductor material includes at least one of group IV-IV, III-V, or II-VI crystalline or compound semiconductor that has a bandgap significantly wider than silicon, wherein the programmable resistive element includes at least one of: (i) a phase-change film in PCRAM, (ii) a resistive thin film in RRAM, or (iii) a magnetic tunnel junction (MTJ) in MRAM. ### Claim 2 (depends on 1) A programmable resistive memory as recited in claim 1, wherein the substrate comprises at least one of silicon, wide bandgap semiconductor, or sapphire. ### Claim 3 (depends on 1) A programmable resistive memory as recited in claim 1, wherein the semiconductor material consists of at least silicon. ### Claim 4 (depends on 1) A programmable resistive memory as recited in claim 1, wherein the selector comprises a MOS device or a diode fabricated with a wide-bandgap semiconductor. ### Claim 5 (depends on 4) A programmable resistive memory as recited in claim 4, wherein the semiconductor material consists of at least one of silicon carbide or gallium nitride. ### Claim 6 A programmable resistive memory integrated with wide-bandgap semiconductor devices, comprising: a plurality of programmable resistive cells, at least one of the cells comprising: a programmable resistive element (PRE) having one end coupled to a first supply voltage line; a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a semiconductor material on a semiconductor or insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line; and a gate fabricated on the layer of the semiconductor material with a sandwich of dielectric in between; the gate coupled to a third supply voltage line, wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state, wherein the semiconductor material includes at least one of group IV-IV, III-V, or II-VI crystalline or compound semiconductor that has a bandgap significantly wider than silicon, and wherein programmable resistive element includes at least one of a one-time-programmable (OTP) element. ### Claim 7 (depends on 6) A programmable resistive memory as recited in claim 6, wherein OTP element comprises at least one of a MOS device to trap charges or to be breakdown in gate oxide to determine the program state. ### Claim 8 (depends on 6) A programmable resistive memory as recited in claim 6, wherein OTP element comprises a metal, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. ### Claim 9 (depends on 6) A programmable resistive memory as recited in claim 6, wherein OTP element has a substantially rectangular shape. ### Claim 10 (depends on 6) A programmable resistive memory as recited in claim 6, wherein OTP element has an OTP body between two nearest contacts in two ends, and has a length-to-width ratio of between 2 to 7 in the OTP body. ### Claim 11 (depends on 6) A programmable resistive memory as recited in claim 6, wherein the OTP element has more contacts in one end than in the other. ### Claim 12 (depends on 6) A programmable resistive memory as recited in claim 6, wherein the OTP element has only one contact in one end. ### Claim 13 An electronics system, comprising: a circuit block fabricated by wide-bandgap semiconductor, and a programmable resistive memory operatively connected to the circuit block, the programmable resistive memory including a plurality of programmable resistive cells, at least one of the cells comprising: a programmable resistive element (PRE) having one end coupled to a first supply voltage line; a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a semiconductor material on a semiconductor or insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line; and a gate fabricated on the layer of semiconductor material with a sandwich of dielectric in between, the gate is coupled to a third supply voltage line and serves to: (i) control the conductivity between the first and the second active region, or (ii) divide the first and second active regions during fabrication, wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state, and wherein the programmable resistive element includes an OTP element that has at least one metal, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. ### Claim 14 (depends on 13) A programmable resistive memory as recited in claim 13, wherein the substrate substantially consists of a silicon, wide-bandgap semiconductor, or sapphire. ### Claim 15 (depends on 13) A programmable resistive memory as recited in claim 13, wherein the semiconductor material substantially consists of at least one of wide-bandgap semiconductor, such as silicon carbide or gallium nitride. ### Claim 16 A method for operating a programmable resistive memory on a semiconductor integrated with wide-bandgap semiconductor devices, the method comprises: providing a plurality of programmable resistive cells, at least one of the programmable resistive cells includes at least (i) a programmable resistive element having one end coupled to a first supply voltage line; and (ii) a selector having at least one first active region and a second active region, both the first and second active regions being fabricated on a semiconductor material on a semiconductor or insulator substrate, the first active region coupled to the programmable resistive element, and the second active region coupled to a second supply voltage line, (iii) a gate fabricated on the semiconductor material with a sandwich of dielectric in between, the gate coupled to a third supply voltage line, the gate provided to separate the first active region from the second active region; determining low and high program thresholds for the wide-bandgap semiconductor; and programming a logic state into at least one of the programmable resistive cells by applying voltages to the first, the second, and/or the third supply voltage lines, wherein the determining of the low and high thresholds comprises: programming a portion of the programmable resistive memory using initially a relatively low program voltage or current and verifying if all the programmable resistive cells in the portion of the programmable resistive memory are programmed; gradually increasing the program voltage or current until all the programmable resistive cells to be programmed in the portion of the programmable resistive memory are programmed and verified correctly, so as to determine the low program threshold for the wide-bandgap semiconductor; and incrementally increasing the program voltage or current and programming a portion of the programmable resistive memory until an excessive voltage or current is identified where at least one of the programmable resistive cells in the portion of the programmable resistive memory, either programmed or not, is verified with an error, so as to determine the high program threshold for the wide-bandgap semiconductor, and wherein the semiconductor material includes at least a wide-bandgap semiconductor. ### Claim 17 (depends on 16) A method as recited in claim 16, wherein the selector comprises a MOS device or a diode fabricated with a wide-bandgap semiconductor. ### Claim 18 (depends on 16) A method as recited in claim 16, wherein the wide-bandgap semiconductor comprises silicon carbide or gallium nitride. ### Claim 19 (depends on 13) A programmable resistive memory as recited in claim 13, wherein the selector comprises a MOS device or a diode fabricated with a wide-bandgap semiconductor, and wherein the third supply voltage line and serves to (i) control conductivity between the first and the second active region in a MOS device configuration, or (ii) divide the first and second active regions during fabrication in a diode device configuration.