# US 12,002,526 B2 · Defect detection during program verify in a memory sub-system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,526 B2 - Document ID: US12002526B2 - Status: Granted - Kind: B2 - Application number: 17/707,766 - Filed: 2022-03-29 - Published: 2022-07-14 - Granted: 2024-06-04 - Earliest claimed: 2020-05-01 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Pinchou Chiang; Arvind Muralidharan; James I. Esteves; Michele Piccardi; Theodore T. Pekny - Web page: https://patentgrep.com/patent/US12002526B2 ## CPC - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 29/025: {in signal lines} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 2029/1202: {Word line control} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition. ## Claims ### Claim 1 A memory device comprising: a memory array comprising a plurality of wordlines; a defect detector circuit coupled to the memory array, wherein the defect detector circuit is configured to sample a load current from a selected wordline of the plurality of wordlines during a program verify phase of a program operation associated with the selected wordline, generate a measured output voltage that modulates with respect to the load current, and perform a comparison of the measured output voltage to a reference voltage; and control logic coupled to the defect detector circuit, wherein the control logic is configured to identify a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the load current on the selected wordline is generated by a program verify voltage applied to the selected wordline. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the defect detector circuit comprises a regulator circuit configured to sample the load current and generate the measured output voltage, wherein the regulator circuit is configured to perform a calibration routine to establish the reference voltage, wherein the reference voltage comprises a reference output voltage of the regulator circuit when the load current is not applied to the regulator circuit. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the regulator circuit comprises a push-pull driver comprising an output stage component, and wherein the measured output voltage represents an operating point of a gate node of the output stage component. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the defect detector circuit comprises a comparator circuit configured to perform the comparison, wherein the comparator circuit is configured to compare the measured output voltage of the regulator circuit to the reference voltage to generate a comparison result. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the comparator circuit is configured to compare the reference voltage to a common mode voltage to generate a first result and to compare the measured output voltage of the regulator circuit to the common mode voltage to generate a second result, wherein the comparison result is based on a difference between the first result and the second result. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the control logic is configured to identify the presence of a defect on the selected wordline when the measured output voltage is less than the reference voltage by at least a threshold amount. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the defect on the selected wordline comprises an electrical short between the selected wordline and an adjacent wordline of the plurality of wordlines in the memory array. ### Claim 9 A method comprising: sampling a load current from a selected wordline of a plurality of wordlines of a memory array of a memory device during a program verify phase of a program operation associated with the selected wordline; generating a measured output voltage that modulates with respect to the load current; performing a comparison of the measured output voltage to a reference voltage; and identifying a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage. ### Claim 10 (depends on 9) The method of claim 9, wherein the load current on the selected wordline is generated by a program verify voltage applied to the selected wordline. ### Claim 11 (depends on 9) The method of claim 9, further comprising: performing a calibration routine to establish the reference voltage, wherein the reference voltage comprises a reference output voltage of a regulator circuit when the load current is not applied to the regulator circuit. ### Claim 12 (depends on 11) The method of claim 11, wherein the regulator circuit comprises a push-pull driver comprising an output stage component, and wherein the measured output voltage represents an operating point of a gate node of the output stage component. ### Claim 13 (depends on 9) The method of claim 9, wherein performing the comparison comprises comparing the measured output voltage to the reference voltage to generate a comparison result, the method further comprising: comparing the reference voltage to a common mode voltage to generate a first result; and comparing the measured output voltage of the regulator circuit to the common mode voltage to generate a second result, wherein the comparison result is based on a difference between the first result and the second result. ### Claim 14 (depends on 9) The method of claim 9, wherein the presence of the defect on the selected wordline is identified when the measured output voltage is less than the reference voltage by at least a threshold amount, and wherein the defect on the selected wordline comprises an electrical short between the selected wordline and an adjacent wordline of the plurality of wordlines in the memory array. ### Claim 15 A memory device comprising: a memory array comprising a plurality of wordlines; a defect detector component operatively coupled with the memory array, to perform operations comprising: sampling a load current from a selected wordline of the plurality of wordlines of the memory array during a program verify phase of a program operation associated with the selected wordline; generating a measured output voltage that modulates with respect to the load current; and performing a comparison of the measured output voltage to a reference voltage; and control logic, operatively coupled with the memory array and the defect detector component, to perform operations comprising: identifying a presence of a defect on the selected wordline in view of the comparison of the measured output voltage to the reference voltage. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the load current on the selected wordline is generated by a program verify voltage applied to the selected wordline. ### Claim 17 (depends on 15) The memory device of claim 15, wherein the defect detector component is to perform operations further comprising: performing a calibration routine to establish the reference voltage, wherein the reference voltage comprises a reference output voltage of a regulator circuit when the load current is not applied to the regulator circuit. ### Claim 18 (depends on 15) The memory device of claim 15, wherein performing the comparison comprises comparing the measured output voltage to the reference voltage to generate a comparison result, and wherein the defect detector circuit is to perform operations further comprising: comparing the reference voltage to a common mode voltage to generate a first result; and comparing the measured output voltage of the regulator circuit to the common mode voltage to generate a second result, wherein the comparison result is based on a difference between the first result and the second result. ### Claim 19 (depends on 15) The memory device of claim 15, wherein the presence of the defect on the selected wordline is identified when the measured output voltage is less than the reference voltage by at least a threshold amount, and wherein the defect on the selected wordline comprises an electrical short between the selected wordline and an adjacent wordline of the plurality of wordlines in the memory array.