# US 12,002,523 B2 · Memory circuit, system and method for rapid retrieval of data sets

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- Number: US 12,002,523 B2
- Document ID: US12002523B2
- Status: Granted
- Kind: B2
- Application number: 17/934,965
- Filed: 2022-09-23
- Published: 2023-01-26
- Granted: 2024-06-04
- Earliest claimed: 2015-09-30
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Eli Harari
- Web page: https://patentgrep.com/patent/US12002523B2

## CPC

- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/063: using electronic means
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5635: {Erasing circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/0491: {Virtual ground arrays}
- G11C 16/10: Programming or data input circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 1/62: Capacitors having potential barriers
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6723: {having light shields}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/037: {comprising charge-trapping insulators}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 43/10: characterised by the top-view layout
- H10D 30/6728: {Vertical TFTs}
- H10D 30/674: {characterised by the active materials}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

## Claims

### Claim 1

A 3-dimensional array of NOR memory strings each comprising a plurality of thin-film storage transistors, the 3-dimensional array comprising first and second groups of data pages, each data page having a predetermined number of storage transistors that are programmed, erased, or read simultaneously, wherein each data page in the second group stores resource management data relating to data in one or more corresponding data pages of the first group, and wherein the resource management data in each data page of the second group is stored or updated in conjunction with programming, erasing or reading of data in each corresponding page of the first group.

### Claim 2 (depends on 1)

The 3-dimensional array of claim 1, wherein the programming, erase, or read operations and the storing and updating of the resource management data are carried out under control of an external controller.

### Claim 3 (depends on 1)

The 3-dimensional array of claim 1, wherein the 3-dimensional array is formed above a planar surface of a semiconductor substrate and wherein each NOR memory string is formed on one of a plurality of planes, each being formed at one of a plurality of predetermined distances above the planar surface.

### Claim 4 (depends on 3)

The 3-dimensional array of claim 3, further comprising a plurality of groups of sense amplifiers, each group of sense amplifiers being formed on an area the semiconductor substrate that is non-overlapping the areas of the other groups of sense amplifiers, wherein storage transistors in each data page in the second group and storage transistors in corresponding data pages in the first group are read using a corresponding group of sense amplifiers.

### Claim 5 (depends on 3)

The 3-dimensional array of claim 3, wherein one or more types of circuits for supporting programming, erase, program-inhibit or read operations in the storage transistors in data pages of the first group are formed at the planar surface of the semiconductor substrate, and wherein the types of circuits comprise one or more of: voltage source, sense amplifiers, data registers, XOR gates and input/output (I/O) terminals.

### Claim 6 (depends on 3)

The 3-dimensional array of claim 3, the NOR memory strings situated within each plane are further organized as blocks.

### Claim 7 (depends on 6)

The 3-dimensional array of claim 6, wherein the NOR memory strings situated within each plane are further organized as quadrants.

### Claim 8 (depends on 7)

The 3-dimensional array of claim 7, wherein NOR memory strings within each quadrant share a predetermined group of circuits for supporting programming, erase, program-inhibit or read operations.

### Claim 9 (depends on 1)

The 3-dimensional array of claim 1, further comprising a third group of data pages providing reference data pages used in conjunction with reading of data pages in the first group.

### Claim 10 (depends on 1)

The 3-dimensional array of claim 1, wherein one or more data pages within the second group serve as spare memory resources to substitute for defective data pages in the first group.

### Claim 11 (depends on 1)

The 3-dimensional array of claim 1, wherein the resource management data comprises one or more of: file management data, configuration parameter values, mapping of addresses of defective data pages to addresses of their replacement data pages, data identifiers, look-up tables, link-lists, timestamps, error detection and error correction data, program-erase cycles of data pages within the first group, optimum voltages and pulse shapes and durations for erase, program, program-inhibit, program scrub, read, margin read, read refresh, read scrub operations, error correcting codes, data recovery modes, and other system parameters.

### Claim 12 (depends on 1)

The 3-dimensional array of claim 1, wherein each data page in the second group and its corresponding data pages in the first group are configured to be activated substantially simultaneously.

### Claim 13 (depends on 1)

The 3-dimensional array of claim 1, further comprising a plurality of conductors each serving as a gate electrode common to a plurality of storage transistors in the NOR memory strings of the 3-dimensional array, wherein conductors serving as gate electrodes for storage transistors within a data page of the second group are shared with storage transistors in a corresponding data page in the first group.

### Claim 14 (depends on 1)

The 3-dimensional array of claim 1 wherein, within each NOR memory string, a first group of storage transistors are configured to be read within a shorter time period than required for reading a second group of storage transistors.

### Claim 15 (depends on 14)

The 3-dimensional array of claim 14, in each NOR memory string having storage transistors belonging to one or more data pages of the second group of data pages, such storage transistors of the second group of data pages belong to the first group of storage transistors.

### Claim 16

A memory circuit formed on a semiconductor substrate that has a substantially planar surface and that includes circuitry formed therein and thereon, the memory circuit comprising a plurality of storage transistors formed over the planar surface, being organized as a plurality of NOR memory strings, each NOR memory string comprising:
(i) a source region and a drain region, each extending along a first direction that is substantially parallel the planar surface;
(ii) a dielectric layer, also extending along the first direction, provided between the source region and the drain region and electrically isolating the source region from the drain region;
(iii) a plurality of channel regions, each channel region being provided over the dielectric layer and in electrical contact with both the source region and the drain region;
(iv) a data storage layer provided over the source region, the drain region and the channel regions; and
(v) a plurality of conductors, each provided next to an associated one of the channel region but separated therefrom by an associated portion of the data storage layer, such that each conductor, serving as a gate electrode, the associated portion of the storage layer, the associated channel region, the source region and the drain region form one of the thin-film storage transistors of the NOR memory string;
wherein one or more voltage sources are formed in the semiconductor substrate for biasing the thin-film transistors of the NOR memory string during a memory operation, and wherein the source region and the drain region each comprise doped semiconductor material, each NOR memory string further comprising a dopant diffusion-blocking layer between the channel regions and one or both of the source region and the drain region.

### Claim 17 (depends on 16)

The memory circuit of claim 16, wherein a separation between the source region and the drain region has a thickness substantially defined by the dielectric layer, and wherein the channel regions are provided after at least a portion of the dielectric layer is removed from between the source region and the drain region.

### Claim 18 (depends on 17)

The memory circuit of claim 17, wherein a portion of the dielectric layer remains between the source region and the drain region to provide mechanical support and electrical isolation.

### Claim 19 (depends on 16)

The memory circuit of claim 16, further comprising:
an isolation layer between the NOR memory strings and the planar surface; and
interconnect conductors embedded in the isolation layer to interconnect the thin-film storage transistors of the NOR memory strings and the circuitry at the planar surface.

### Claim 20 (depends on 19)

The memory circuit of claim 19, further comprising buried contacts formed in the isolation layer to electrically connect the drain regions of the NOR memory strings to the circuitry.

### Claim 21 (depends on 16)

The memory circuit of claim 16, wherein the data storage layer comprises a tunnel dielectric film and one or more layers of charge-trapping material each selected from silicon nitride, silicon-rich silicon nitride, silicon oxide, nanocrystals, nanodots embedded in a thin dielectric film, or isolated floating gates, wherein each layer of charge-trapping material is being provided between blocking dielectric films each selected from a silicon dioxide film, an ONO layer, a high dielectric constant film of materials including aluminum oxide, hafnium oxide or some combination thereof.

### Claim 22 (depends on 21)

The memory circuit of claim 21, wherein the tunnel dielectric layer comprises one or more of a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide (“ONO”) triple layer, a bandgap engineered dielectric and a silicon nitride layer.

### Claim 23 (depends on 21)

The memory circuit of claim 21, wherein each storage transistor is configured to be programmed or erase by direct tunneling through the tunnel dielectric film between the charge-trapping material and the associated channel region of the storage transistor.

### Claim 24 (depends on 16)

The memory circuit of claim 16, wherein the source region, the drain region and the channel regions are aligned to provide a sidewall in a plane substantially normal to the planar surface.

### Claim 25 (depends on 24)

The memory circuit of claim 24, wherein the channel regions are formed out of a conformal layer deposited over cavities form in the dielectric layer.

### Claim 26 (depends on 16)

The memory circuit of claim 16, wherein the source region is electrically connected to one of the voltage sources during a first phase of the memory operation but is electrically isolated from the voltage sources in the remainder of the memory operation.