# US 12,002,521 B2 · Memory device error detection with improved scanning > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,521 B2 - Document ID: US12002521B2 - Status: Granted - Kind: B2 - Application number: 17/470,550 - Filed: 2021-09-09 - Published: 2021-12-30 - Granted: 2024-06-04 - Earliest claimed: 2018-12-28 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Giuseppe Cariello - Web page: https://patentgrep.com/patent/US12002521B2 ## CPC - G11C 16/3422: {Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem} - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device may include memory cells configured to establish multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells. The operations may include recording a bit count number for a highest level of charge distributions within a set of memory cells, recording a bit count number for a lowest level of charge distributions within the set of memory cells, counting bits for the highest level of charge distributions within the set of memory cells, counting bits in the lowest level of charge distributions within the set of memory cells, comparing the counted bits for the highest level to the recorded bit count number for the highest level, and comparing the counted bits for the lowest level to the recorded bit count number for the lowest level. ## Claims ### Claim 1 A method, comprising: programming memory cells using multiple levels of charge distributions, wherein the memory cells are multi-level cells (MLCs), and each of the MLCs are capable of representing more than one bit of data using the multiple levels of charge distributions; assessing reliability for at least one page of MLCs without applying error correction code (ECC) by: recording a bit count number for a highest level of charge distributions or a lowest level of charge distributions within the at least one page of MLCs; counting bits for the highest level of charge distributions or for the lowest level of charge distributions within the at least one page of MLCs without counting bits for all of the multiple levels of charge distributions; comparing the counted bits to the recorded bit count number; and determining the at least one page of MLCs is not reliable only when the counted bits and the recorded bit count number are not equal; and in response to determining that the at least one page of MLCs is not reliable, performing operations to recover programmed data. ### Claim 2 (depends on 1) The method of claim 1, wherein firmware is used to record the bit count number for the highest level of charge distributions or the lowest level of charge distributions. ### Claim 3 (depends on 1) The method of claim 1, wherein the recorded bit count number is indicative of a bit count when the memory cells were programmed. ### Claim 4 (depends on 1) The method of claim 1, further comprising using strobes to control timing for data transfers, wherein the bits for the highest level of charge distributions and the bits in the lowest level of charge distributions are counted in one strobe. ### Claim 5 (depends on 1) The method of claim 1, wherein the determining does not use an Error Correction Code (ECC) engine. ### Claim 6 (depends on 1) The method of claim 1, wherein the multiple levels of charge distributions include at least four levels of charge distributions for representing at least two bits of data per memory cell. ### Claim 7 A method, including: programing memory cells using multiple levels of charge distributions, wherein the memory cells are multi-level cells (MLCs), and each of the MLCs are capable of representing more than one bit of data using the multiple levels of charge distributions; assessing reliability for at least one page of MLCs without applying error correction code (ECC) by: recording a bit count number for a highest level of charge distribution within the at least one page of MLCs; and counting bits for the highest level of charge distributions within the at least one page of MLCs without counting bits for all of the multiple levels of charge distributions; comparing the counted bits to the recorded bit count number; and determining the at least one page of MLCs is not reliable only when the counted bits are not equal to the recorded bit count number and in response to determining that the at least one page of MLCs is not reliable, performing operations to recover programmed data. ### Claim 8 (depends on 7) The method of claim 7, wherein firmware is used to record the bit count number for the highest level of charge distribution. ### Claim 9 (depends on 7) The method of claim 7, wherein the recorded bit count number for the highest level of charge distributions is indicative of a bit count for the highest level of charge distribution when the memory cells were programmed. ### Claim 10 (depends on 7) The method of claim 7, wherein the multiple levels of charge distributions include at least four levels of charge distributions for representing at least two bits of data per memory cell. ### Claim 11 A method, including: programing memory cells using multiple levels of charge distributions, wherein the memory cells are multi-level cells (MLCs), and each of the MLCs are capable of representing more than one bit of data using the multiple levels of charge distributions; assessing reliability for at least one page of MLCs without applying error correction code (ECC) by: recording a bit count number for a lowest level of charge distribution within the at least one page of MLCs; and counting bits for the lowest level of charge distributions within the at least one page of MLCs without counting bits for all of the multiple levels of charge distributions; comparing the counted bits to the recorded bit count number; and determining the at least one page of MLCs is not reliable only when the counted bits are not equal to the recorded bit count number; and in response to determining that the at least one page of MLCs is not reliable, performing operations to recover programmed data. ### Claim 12 (depends on 11) The method of claim 11, wherein firmware is used to record the bit count number for the lowest level of charge distribution. ### Claim 13 (depends on 11) The method of claim 11, wherein the recorded bit count number for the lowest level of charge distributions is indicative of a bit count for the lowest level of charge distribution when the memory cells were programmed. ### Claim 14 (depends on 11) The method of claim 11, wherein the multiple levels of charge distributions include at least four levels of charge distributions for representing at least two bits of data per memory cell. ### Claim 15 A memory device, comprising: memory cells configured to establish multiple levels of charge distributions, wherein the memory cells are multi-level cells (MLCs), and each of the MLCs are capable of representing more than one bit of data using the multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells, the operations including: program the MLCs; assess reliability for at least one page of MLCs without applying error correction code (ECC) by: recording a data set, the data set including a bit count number for at least one of a highest level of charge distributions or a lowest level of charge distributions within the at least one page of MLCs; and counting bits for the highest level of charge distributions or for the lowest level of charge distributions within the at least one page of MLCs without counting bits for all of the multiple levels of charge distributions; comparing the counted bits to the recorded bit count number; and determining the at least one page of MLCs is not reliable only when the counted bits and the recorded bit count number are not equal; and perform operations to recover programmed data in response to determining that the at least one page of MLCs is not reliable. ### Claim 16 (depends on 15) The memory device of claim 15, wherein the data error includes a read disturb or a write disturb, wherein the recorded bit count number and the counted bits correspond to the lowest level of charge distributions. ### Claim 17 (depends on 15) The memory device of claim 15, wherein the data error includes charge leakage, wherein the recorded bit count number and the counted bits correspond to the highest level of charge distributions. ### Claim 18 (depends on 15) The memory device of claim 15, further comprising using firmware to count bits and to compare the counted bits. ### Claim 19 (depends on 15) The memory device of claim 15, wherein firmware is used to count bits and compare the counted bits to the recorded bit count number. ### Claim 20 A system, comprising: a host controller configured to serially communicate with a memory device; and the memory device includes memory cells and a memory controller configured to perform operations on the memory cells, the memory cells being configured to establish multiple levels of charge distributions, wherein the memory cells are multi-level cells (MLCs) and each of the MLCs are capable of representing more than one bit of data using the multiple levels of charge distributions, the operations including: program the MLCs; assess reliability for at least one page of MLCs without applying error correction code (ECC) by: recording a data set, the data set including a bit count number for at least one of a highest level of charge distributions or a lowest level of charge distributions within the at least one page of MLCs; and using firmware to count bits for the highest level of charge distributions or for the lowest level of charge distributions within the at least one page of MLCs without counting bits for all of the multiple levels of charge distributions, to compare the counted bits to the recorded bit count number, and to determine the at least one page of MLCs is not reliable only when the counted bits and the recorded bit count number are not equal; and perform operations to recover programmed data in response to determining that the at least one page of MLCs is not reliable. ### Claim 21 (depends on 20) The system of claim 20, wherein the data error includes a read disturb or a write disturb, wherein the recorded bit count number and the counted bits correspond to the lowest level of charge distributions. ### Claim 22 (depends on 20) The system of claim 20, wherein the data error includes charge leakage, wherein the recorded bit count number and the counted bits correspond to the highest level of charge distributions.