# US 12,002,513 B2 · Self-annealing data storage system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,513 B2 - Document ID: US12002513B2 - Status: Granted - Kind: B2 - Application number: 17/567,401 - Filed: 2022-01-03 - Published: 2022-07-28 - Granted: 2024-06-04 - Earliest claimed: 2006-11-29 - Assignees: Rambus Inc. - Applicants: Rambus Inc. - Inventors: Gary B. Bronner; Brent Steven Haukness; Mark A. Horowitz; Mark D. Kellam; Fariborz Assaderaghi - Web page: https://patentgrep.com/patent/US12002513B2 ## CPC - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 7/04: with means for avoiding disturbances due to temperature effects - H10P 95/90: Thermal treatments, e.g. annealing or sintering - G11C: STATIC STORES (semiconductor memory devices H10B) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa. ## Claims ### Claim 1 A data storage system comprising: non-volatile semiconductor memories; and control circuitry to detect, during operation of the data storage system, an event indicating use-related degradation of one or more of the non-volatile semiconductor memories and, in response to detecting the event, to heat the one or more non-volatile semiconductor memories to counteract the use-related degradations, wherein the control circuitry to detect the event indicating use-related degradation of the one or more of the non-volatile semiconductor memories comprises circuitry to detect that a threshold number of performance-degrading operations have been executed within the one or more of the non-volatile semiconductor memories. ### Claim 2 (depends on 1) The data storage system of claim 1 wherein the non-volatile semiconductor memories are disposed within respective integrated-circuit dies. ### Claim 3 (depends on 2) The data storage system of claim 2 wherein data storage system implements, at least in part, a solid-state storage drive (SSD) containing the integrated-circuit dies. ### Claim 4 (depends on 2) The data storage system of claim 2 wherein the data storage system comprises a memory-module substrate having an edge connector and having the integrated-circuit dies disposed one at least one face of the memory-module substrate and conductively coupled to the edge connector to implement a memory module that may be removably inserted into a memory-module receptacle of a data processing system. ### Claim 5 (depends on 2) The data storage system of claim 2 wherein the control circuitry comprises a plurality of heat generating circuits disposed respectively within the integrated-circuit dies to enable heating of respective ones of the non-volatile semiconductor memories. ### Claim 6 (depends on 2) The data storage system of claim 2 wherein the control circuitry comprises a plurality of heat generating circuits disposed adjacent respective ones of the integrated-circuit dies to enable heating of respective ones of the non-volatile semiconductor memories. ### Claim 7 (depends on 1) The data storage system of claim 1 wherein the non-volatile semiconductor memories comprise non-volatile storage cells that exhibit, as an aspect of use-related degradation, progressively degraded data retention times as programming operations are executed to stored data within the non-volatile storage cells. ### Claim 8 (depends on 7) The data storage system of claim 7 wherein the non-volatile storage cells comprise floating-gate field-effect-transistor storage elements. ### Claim 9 (depends on 1) The data storage system of claim 1, wherein the circuitry to detect that the threshold number of performance-degrading operations have been executed comprises a programmable register and circuitry to store a value indicative of the threshold number of performance-degrading operations within the programmable register upon receiving the value from a source external to the data storage system. ### Claim 10 A data storage system comprising: non-volatile semiconductor memories; and control circuitry to detect, during operation of the data storage system, an event indicating use-related degradation of one or more of the non-volatile semiconductor memories and, in response to detecting the event, to heat the one or more non-volatile semiconductor memories to counteract the use-related degradation; wherein the circuitry to detect the event indicating use-related degradation of the one or more of the non-volatile semiconductor memories comprises circuitry to determine that a threshold quantity of errors have been detected during operation of the non-volatile semiconductor memories. ### Claim 11 (depends on 10) The data storage system of claim 10 wherein the circuitry to determine that the threshold quantity of errors have been detected during operation of the non-volatile semiconductor memories comprises circuitry to determine that the threshold quantity of errors have been detected within a time interval such that a threshold error rate has been reached. ### Claim 12 A method of operation within a data storage system, the method comprising: detecting an event indicating use-related degradation of one or more of the non-volatile semiconductor memories within the data storage system; and, in response to detecting the event, heating the one or more non-volatile semiconductor memories to counteract the use-related degradation; wherein detecting the event indicating use-related degradation of the one or more of the non-volatile semiconductor memories comprises detecting that a threshold number of performance-degrading operations have been executed within the one or more of the non-volatile semiconductor memories. ### Claim 13 (depends on 12) The method of claim 12 wherein the one or more non-volatile semiconductor memories are disposed within respective integrated-circuit dies. ### Claim 14 (depends on 13) The method of claim 13 wherein the integrated-circuit dies constitute, at least in part, a data storage memory within a solid-state storage drive (SSD). ### Claim 15 (depends on 13) The method of claim 13 wherein the integrated-circuit dies are disposed on at least one face of a memory-module substrate having an edge connector conductively coupled to the integrated-circuit dies. ### Claim 16 A method of operation within a data storage system, the method comprising: detecting an event indicating use-related degradation of one or more of the non-volatile semiconductor memories within the data storage system; and, in response to detecting the event, heating the one or more non-volatile semiconductor memories to counteract the use-related degradation; wherein the one or more non-volatile semiconductor memories are disposed within respective integrated-circuit dies; wherein heating the one or more non-volatile semiconductor memories to counteract the use-related degradation comprises activating one or more heat generating circuits disposed respectively within the integrated-circuit dies. ### Claim 17 A method of operation within a data storage system, the method comprising: detecting an event indicating use-related degradation of one or more of the non-volatile semiconductor memories within the data storage system; and, in response to detecting the event, heating the one or more non-volatile semiconductor memories to counteract the use-related degradation; wherein the one or more non-volatile semiconductor memories are disposed within the respective integrated-circuit dies; wherein heating the one or more non-volatile semiconductor memories to counteract the use-related degradation comprises activating one or more heat generating circuits disposed adjacent respective ones of the integrated-circuit dies. ### Claim 18 A method of operation within a data storage system, the method comprising: detecting an event indicating use-related degradation of one or more of the non-volatile semiconductor memories within the data storage system; and, in response to detecting the event, heating the one or more non-volatile semiconductor memories to counteract the use-related degradation; wherein the event indicating use-related degradation of the one or more of the non-volatile semiconductor memories comprises determining that a threshold quantity of errors have been detected during operation of the non-volatile semiconductor memories.