# US 12,002,510 B2 · Program current controller and sense circuit for cross-point memory devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,002,510 B2
- Document ID: US12002510B2
- Status: Granted
- Kind: B2
- Application number: 17/588,718
- Filed: 2022-01-31
- Published: 2023-08-03
- Granted: 2024-06-04
- Earliest claimed: 2022-01-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Andrea Ghetti; Andrea Martinelli; Efrem Bolandrina; Ferdinando Bedeschi; Paolo Fantini
- Web page: https://patentgrep.com/patent/US12002510B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0009: {RRAM elements whose operation depends upon chemical change}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2213/15: Current-voltage curve
- G11C 2213/30: Resistive cell, memory material aspects
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.

## Claims

### Claim 1

A device comprising:
a digit line decoder configured to select a digit line for accessing a memory cell;
a controller configured to select operation in a first program polarity or a second program polarity, wherein the first and second program polarities are opposite; and
first circuitry coupled between a first voltage supply and the digit line decoder, the first circuitry configured to sense a characteristic associated with the memory cell, and limit a current through the memory cell when operating in the first program polarity.

### Claim 2 (depends on 1)

The device of claim 1, further comprising second circuitry coupled between a second voltage supply and the digit line decoder, the second circuitry configured to sense the characteristic associated with the memory cell, and limit the current through the memory cell when operating in the second program polarity, wherein:
the first and second voltage supplies are of opposite polarity;
the characteristic is the current through the memory cell;
the first circuitry comprises a current limiter to limit the current, and a sense amplifier to sense the current; and
the second circuitry comprises a current limiter to limit the current, and a sense amplifier to sense the current.

### Claim 3 (depends on 2)

The device of claim 2, wherein the current passes through the first circuitry when operating in the first program polarity, and the current passes through the second circuitry when operating in the second program polarity.

### Claim 4 (depends on 2)

The device of claim 2, further comprising a wordline decoder configured to select a wordline for accessing the memory cell, wherein:
the first voltage supply has a first polarity;
the second voltage supply has a second polarity;
the wordline decoder is further configured to apply a voltage of the second polarity to the wordline when operating in the first program polarity; and
the wordline decoder is further configured to apply a voltage of the first polarity to the wordline when operating in the second program polarity.

### Claim 5 (depends on 4)

The device of claim 4, wherein a capacitance of the wordline is at least 100 times greater than a capacitance of the digit line.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a wordline decoder configured to select a wordline for accessing the memory cell, wherein:
the digit line decoder is a first digit line decoder of a plurality of digit line decoders;
the memory cell is a first memory cell of a plurality of memory cells;
the wordline is further configured to simultaneously select the memory cells during a read operation; and
each of the memory cells is selected by a respective one of the digit line decoders during the read operation.

### Claim 7 (depends on 1)

The device of claim 1, wherein the memory cell comprises chalcogenide.

### Claim 8 (depends on 1)

The device of claim 1, wherein the memory cell snaps after being accessed during a read or write operation, and the current is limited by a current limiter after the memory cell snaps.

### Claim 9 (depends on 1)

The device of claim 1, wherein the memory cell exhibits an S-shaped current-voltage (I-V) characteristic curve.

### Claim 10

An apparatus comprising:
a memory array;
a wordline decoder configured to apply a voltage to a wordline for accessing first memory cells in the memory array, wherein the wordline decoder is further configured to operate in a first program polarity or a second program polarity, and wherein the first and second program polarities are opposite;
a plurality of digit line decoders, each digit line decoder configured to apply a voltage to a respective digit line for accessing a respective one of the first memory cells; and
a plurality of switches configured to couple each digit line decoder to a respective first sensing circuit when operating in the first program polarity, or to a respective second sensing circuit when operating in the second program polarity.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein:
the first sensing circuit is configured to couple a first supply voltage to the respective digit line decoder;
the first sensing circuit is further configured to sense a current associated with the respective first memory cell, and limit the current;
the second sensing circuit is configured to couple a second supply voltage to the respective digit line decoder, wherein the first and second supply voltages are of opposite polarity; and
the second sensing circuit is further configured to sense the current associated with the respective first memory cell, and limit the current.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein each of the first memory cells comprises chalcogenide.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein each of the first memory cells snaps after being accessed during a read or write operation, and a current is limited for each respective memory cell after the memory cell snaps.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein each of the first memory cells exhibits an S-shaped current-voltage (I-V) characteristic curve.

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the first sensing circuit is configured to regulate the voltage applied to the respective digit line, and the second sensing circuit is configured to regulate the voltage applied to the respective digit line.

### Claim 16 (depends on 10)

The apparatus of claim 10, wherein a current is sensed by the first or second sensing circuit as part of a read operation to determine a logic state of the respective first memory cell.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the read operation is performed by a controller in response to receiving a read command from a host device.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the current sensed by the first or second sensing circuit is a current through the respective first memory cell.

### Claim 19

A method comprising:
applying, by digit line decoders, a voltage to respective digit lines for accessing a respective one of first memory cells;
selecting, by a controller, a program polarity to be a first program polarity or a second program polarity, wherein the first and second program polarities are opposite; and
coupling, based on the selected program polarity, each digit line decoder to a respective first sensing circuit when the first program polarity is selected, or to a respective second sensing circuit when the second program polarity is selected.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
applying, by a wordline decoder, a voltage to a wordline for accessing the first memory cells, wherein the wordline decoder is configured to operate in the first program polarity or the second program polarity.

### Claim 21 (depends on 19)

The method of claim 19, wherein:
the first sensing circuit is configured to couple a first supply voltage to the respective digit line decoder;
the second sensing circuit is configured to couple a second supply voltage to the respective digit line decoder; and
the first and second supply voltages are of opposite polarity.

### Claim 22 (depends on 21)

The method of claim 21, wherein:
the first sensing circuit is further configured to sense a current associated with the respective first memory cell, and limit the current; and
the second sensing circuit is further configured to sense the current associated with the respective first memory cell, and limit the current.

### Claim 23 (depends on 19)

The method of claim 19, wherein each of the first memory cells snaps after being accessed during a read or write operation.

### Claim 24

A non-transitory computer-readable medium storing instructions which, when executed by a controller, cause the controller to:
select a first access line for accessing a memory cell;
select, using a decoder, a second access line for accessing the memory cell;
select operation in a first program polarity or a second program polarity, wherein the first and second program polarities are opposite; and
for operation in either of the selected first or second program polarity, sense a current through the decoder, and limit the current.

### Claim 25 (depends on 24)

The non-transitory computer-readable medium of claim 24, wherein the first access line is a wordline, the second access line is a digit line, and the decoder is a digit line decoder.

### Claim 26 (depends on 25)

The non-transitory computer-readable medium of claim 25, wherein a capacitance of the wordline is at least 100 times greater than a capacitance of the digit line.

### Claim 27 (depends on 24)

The non-transitory computer-readable medium of claim 24, wherein respective structures of the first access line and the second access line are asymmetric.

### Claim 28 (depends on 27)

The non-transitory computer-readable medium of claim 27, wherein:
the memory cell is accessed as part of a programming operation in which more than one memory cell is programmed in parallel along the first access line; and
sensing the current is part of a sense operation associated with the second access line, but not the first access line.

### Claim 29 (depends on 24)

The non-transitory computer-readable medium of claim 24, wherein the current is sensed by a selected first or second sensing circuit, coupled to the decoder, as part of a read or write operation.

### Claim 30 (depends on 29)

The non-transitory computer-readable medium of claim 29, wherein the read or write operation is performed in response to receiving a read or write command from a host device.