# US 12,002,509 B2 · Data readout circuit of resistive random access memory and resistive random access memory circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,509 B2 - Document ID: US12002509B2 - Status: Granted - Kind: B2 - Application number: 17/756,315 - Filed: 2021-07-02 - Published: 2024-05-09 - Granted: 2024-06-04 - Earliest claimed: 2021-04-23 - Assignees: Institute of Microelectronics, Chinese Academy of Sciences - Applicants: Institute of Microelectronics of the Chinese Academy of Sciences - Inventors: Feng Zhang; Qirui Ren - Web page: https://patentgrep.com/patent/US12002509B2 ## CPC - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0059: {Security or protection circuits or methods} - G11C 2013/0045: {Read using current through the cell} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data readout circuit of a RRAM includes: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM. ## Claims ### Claim 1 A data readout circuit of a resistive random access memory (RRAM), comprising: an adaptive current sense amplifier (CSA) and a reference current generator, wherein the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current based on the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare a size of the reference current and that of the bit-line current so as to read out data stored in the RRAM; wherein the adaptive CSA comprises a data readout module and a reference current module; the data readout module is electrically connected to the reference current module, and the data readout module is configured to electrically connect to the RRAM, and the reference current module is electrically connected to the RRAM and the reference current generator respectively; the reference current module is configured to obtain the reference current based on the basic reference current and the bit-line current; and the data readout module is configured to compare the size of the reference current and that of the bit-line current, so as to read out the stored data. ### Claim 2 (depends on 1) The data readout circuit of the RRAM according to claim 1, wherein the reference current module comprises a feedback unit and a plurality of amplifying units; the feedback unit is electrically connected to the RRAM and the amplifying units respectively, and each of the amplifying units is electrically connected to the data readout module and the reference current generator respectively; the feedback unit is configured to generate an challenge response according to the bit-line current of the RRAM, and control conduction of a corresponding amplifying unit according to the challenge response; and the amplifying unit is configured to amplify the basic reference current to obtain a corresponding reference current. ### Claim 3 (depends on 2) The data readout circuit of the RRAM according to claim 2, wherein the plurality of amplifying units are connected in parallel, and each of the amplifying units has a corresponding amplification factor. ### Claim 4 (depends on 3) The data readout circuit of the RRAM according to claim 3, wherein each of the amplifying units includes a first MOS transistor, and a gate of the first MOS transistor is electrically connected to the feedback unit. ### Claim 5 (depends on 3) The data readout circuit of the RRAM according to claim 3, wherein each of the amplifying units includes a second MOS transistor, and a third MOS transistor is disposed between the second MOS transistor and the reference current generator; a width-to-length ratio of a channel of the third MOS transistor multiplied by the amplification factor is equal to a width-to-length ratio of a channel of a corresponding second MOS transistor. ### Claim 6 (depends on 1) The data readout circuit of the RRAM according to claim 1, wherein the adaptive CSA includes a pre-protection module; the data readout module includes a bit-line current input terminal, a reference current input terminal and a data readout terminal; and the bit-line current input terminal and the reference current input terminal are respectively electrically connected to the pre-protection module. ### Claim 7 (depends on 1) The data readout circuit of the RRAM according to claim 1, wherein the reference current generator includes a replica resistive random access memory module and a current generation module; the current generation module is configured to generate the basic reference current when the replica resistive random access memory module is in a low resistance state, wherein a current when the replica resistive random access memory module is in the low resistance state is a low resistance current which is twice the basic reference current. ### Claim 8 (depends on 7) The data readout circuit of the RRAM according to claim 7, wherein the replica resistive random access memory module includes a plurality of resistive random access memory cells. ### Claim 9 (depends on 1) A resistive random access memory circuit, comprising: a RRAM and the data readout circuit of the RRAM according to claim 1; the RRAM includes a resistive random access memory array and a data writing control circuit, and the resistive random access memory array is electrically connected to the data writing control circuit; the resistive random access memory array is electrically connected to the data readout circuit of the RRAM; and the resistive random access memory array includes a plurality of resistive random access memory cells.