# US 12,002,507 B2 · Static random access memory with adaptive precharge signal generated in response to tracking operation

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- Number: US 12,002,507 B2
- Document ID: US12002507B2
- Status: Granted
- Kind: B2
- Application number: 18/068,881
- Filed: 2022-12-20
- Published: 2023-04-20
- Granted: 2024-06-04
- Earliest claimed: 2020-11-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited; Tsmc China Company Limited
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; TSMC Nanjing Company Limited; TSMC China Company Limited
- Inventors: Xiu-Li Yang; He-Zhou Wan; Lu-Ping Kong; Wei-Yang Jiang
- Web page: https://patentgrep.com/patent/US12002507B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 7/08: Control thereof
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 2207/2281: Timing of a read operation
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.

## Claims

### Claim 1

A device, comprising:
a plurality of transistors coupled to a tracking bit line and configured to generate a first tracking signal;
a sense circuit configured to generate a first sense tracking signal in response to the first tracking signal; and
a precharge circuit configured to generate, in response to a falling edge of the first sense tracking signal, a precharge signal having a falling edge, wherein the precharge signal is for precharging data lines.

### Claim 2 (depends on 1)

The device of claim 1, wherein gate terminals of the plurality of transistors are coupled together to a tracking word line and configured to receive a word line tracking signal.

### Claim 3 (depends on 1)

The device of claim 1, wherein the plurality of transistors include:
a first transistor of a first conductivity type, a first terminal of the first transistor being configured to receive a reference voltage; and
at least one second transistor of a second conductivity type, a first terminal of the at least one second transistor being configured to receive a ground voltage;
wherein the first conductivity type and the second conductivity type are different from each other, and second terminals of the first transistor and the at least one second transistor are coupled together to the tracking bit line.

### Claim 4 (depends on 3)

The device of claim 3, wherein gate terminals of first transistor and the at least one second transistor are coupled together to a tracking word line and configured to receive a word line tracking signal.

### Claim 5 (depends on 4)

The device of claim 4, wherein the at least one second transistor is configured to pull down, in response to the word line tracking signal being at logic high, a voltage of the first tracking signal.

### Claim 6 (depends on 1)

The device of claim 1, wherein an amount of the plurality of transistors is substantially equal to an amount of cell rows in a memory array.

### Claim 7 (depends on 1)

The device of claim 1, wherein the sense circuit comprises:
a first transistor;
a second transistor; and
a third transistor;
wherein the first transistor, the second transistor, and the third transistor are coupled in series between a reference voltage and a ground voltage.

### Claim 8 (depends on 7)

The device of claim 7, wherein the sense circuit further comprises:
a fourth transistor,
wherein a first terminal of the fourth transistor, a first terminal of the first transistor, and a first terminal of the second transistor are coupled together, and a gate terminal of the fourth transistor, a second terminal of the second transistor, and a first terminal of the third transistor are coupled together to the precharge circuit.

### Claim 9 (depends on 7)

The device of claim 7, wherein gate terminals of the first transistor, the second transistor, and the third transistor are coupled together to receive the first tracking signal.

### Claim 10

A device, comprising:
a first sense circuit configured to generate a first sense tracking signal in response to a first tracking signal that is associated with a plurality of first tracking cells;
a second sense circuit configured to generate a second sense tracking signal in response to a second tracking signal that is associated with a plurality of second tracking cells; and
a control circuit configured to:
generate, in response to the first sense tracking signal, a precharge signal for precharging data lines; and
generate, in response to the second sense tracking signal, a sense enable signal for enabling a sense amplifier circuit.

### Claim 11 (depends on 10)

The device of claim 10, further comprising:
a first plurality of transistors coupled to the first sense circuit and configured to generate the first tracking signal; and
a second plurality of transistors coupled to the second sense circuit and configured to generate the second tracking signal.

### Claim 12 (depends on 11)

The device of claim 11, wherein an amount of the second plurality of transistors is less than an amount of the first plurality of transistors.

### Claim 13 (depends on 11)

The device of claim 11, wherein each of the first plurality of transistors and the second plurality of transistors includes:
a first transistor of a first conductivity type, a first terminal of the first transistor being configured to receive a reference voltage; and
at least one second transistor of a second conductivity type, a first terminal of the at least one second transistor being configured to receive a ground voltage;
wherein the first conductivity type and the second conductivity type are different from each other, and second terminals of the first transistor and the at least one second transistor are coupled together.

### Claim 14 (depends on 13)

The device of claim 13, wherein
gate terminals of first transistor and the at least one second transistor are coupled together to receive a word line tracking signal; and
in response to the word line tracking signal being at logic high, the at least one second transistor is configured to pull down a voltage of the first tracking signal and a voltage of the second tracking signal.

### Claim 15 (depends on 10)

The device of claim 10, wherein each of the first sense circuit and the second sense circuit comprises:
a first transistor of a first conductivity type;
a second transistor of the first conductivity type;
a third transistor of a second conductivity type; and
a fourth transistor of the first conductivity type;
wherein the first transistor, the second transistor, and the third transistor are coupled in series between a reference voltage and a ground voltage.

### Claim 16 (depends on 10)

The device of claim 10, wherein the control circuit is further configured to:
pulling low, in response to a falling edge of a read enable delayed signal, the precharge signal; and
generate, in response to the read enable delayed signal, the sense enable signal;
wherein the read enable delayed signal is associated with a read enable signal.

### Claim 17

A method, comprising:
generating a first tracking signal that is associated with a first plurality of transistors coupled to a first tracking bit line;
in response to the first tracking signal being at logic low, generating a first sense tracking signal that is at logic high; and
in response to a falling edge of the first sense tracking signal, generating a precharge signal having a falling edge, wherein the precharge signal is for precharging data lines.

### Claim 18 (depends on 17)

The method of claim 17, wherein generating the first tracking signal comprises:
generating a word line tracking signal that is associated with a clock signal; and
in response to the word line tracking signal being at logic high, discharging a voltage of the first tracking signal by the first plurality of transistors.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
generating a read enable delayed signal that is associated with a read enable signal; and
pulling low the precharge signal in response to a falling edge of the read enable delayed signal.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
generating a second tracking signal that is associated with a second plurality of transistors coupled to a second tracking bit line;
in response to the second tracking signal being at logic low, generating a second sense tracking signal that is at logic high; and
in response to the second sense tracking signal, generating a sense enable signal for enabling a sense amplifier circuit.