# US 12,002,506 B2 · Buffered dynamic random access memory device

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- Number: US 12,002,506 B2
- Document ID: US12002506B2
- Status: Granted
- Kind: B2
- Application number: 17/728,638
- Filed: 2022-04-25
- Published: 2022-11-17
- Granted: 2024-06-04
- Earliest claimed: 2021-05-13
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Torsten Partsch
- Web page: https://patentgrep.com/patent/US12002506B2

## CPC

- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.

## Claims

### Claim 1

A DRAM component, comprising:
a first interface to receive first data to be written to a first DRAM memory array and second data retrieved from a second DRAM memory array;
a second interface to receive command/address signals;
the first interface being configurable to, based on configuration information, retransmit zero or more of the first data and the second data and being configurable to, based on the configuration information, not retransmit zero or more of the first data and the second data; and,
the second interface being configurable to, based on the configuration information, retransmit the command/address signals and being configurable to, based on the configuration information, not retransmit the command/address signals.

### Claim 2 (depends on 1)

The DRAM component of claim 1, wherein the first interface includes a first unidirectional signal group to receive the first data and a second unidirectional signal group to retransmit the first data and a third unidirectional signal group to receive the second data and a fourth unidirectional signal group to retransmit the second data.

### Claim 3 (depends on 1)

The DRAM component of claim 1, further comprising:
a third interface to receive the configuration information used to determine whether the first interface is configured to retransmit zero or more of the first data and the second data and to determine whether the first interface is configured not to retransmit zero or more of the first data and the second data, the configuration information to also determine whether the second interface is configured to retransmit the command/address signals and to determine whether the second interface is configured to not retransmit the command/address signals.

### Claim 4 (depends on 1)

The DRAM component of claim 1, wherein the DRAM component is to perform a combined activate (ACT) and read (RD) command received via the command/address signals and is to perform a combined activate (ACT) and write (WR) command received via the command/address signals.

### Claim 5 (depends on 1)

The DRAM component of claim 1, wherein the DRAM component is to perform a burst command received via the command/address signals that indicates a burst start and a burst end that are directed to a same row of a DRAM memory array of the DRAM component.

### Claim 6 (depends on 1)

The DRAM component of claim 1, further comprising:
a third interface to transmit a first timing reference signal for a synchronous reception of data transmitted by the first interface.

### Claim 7 (depends on 6)

The DRAM component of claim 6, wherein the first timing reference signal is a retransmitted version of a second timing reference signal received from another DRAM component.

### Claim 8 (depends on 1)

The DRAM component of claim 1, wherein the first interface communicates error correction and detection information, and the second interface communicates error detection information.

### Claim 9

A DRAM memory device, comprising:
a data interface to receive data signals;
a command/address interface to receive command/address signals; and,
the data interface configurable, in a first data (DQ) interface mode, to retransmit received data signals, the command/address (CA) interface configurable, in a first CA interface mode, to retransmit received command/address signals.

### Claim 10 (depends on 9)

The DRAM memory device of claim 9, wherein the data interface is configurable, in a second DQ interface mode, to not retransmit received data signals.

### Claim 11 (depends on 9)

The DRAM memory device of claim 9, wherein the CA interface is configurable, in a second CA interface mode, to not retransmit received command/address signals.

### Claim 12 (depends on 11)

The DRAM memory device of claim 11, wherein the CA interface comprises a first unidirectional CA interface to receive first CA signals and a second unidirectional CA interface to retransmit the first CA signals.

### Claim 13 (depends on 12)

The DRAM memory device of claim 12, wherein whether the second unidirectional CA interface to retransmits the first CA signals is determined by a second CA interface mode.

### Claim 14 (depends on 9)

The DRAM memory device of claim 9, wherein the data interface comprises a first unidirectional data interface to receive first data signals and a second unidirectional data interface to retransmit the first data signals.

### Claim 15 (depends on 14)

The DRAM memory device of claim 14, wherein the data interface comprises a third unidirectional data interface to receive second data signals and a fourth unidirectional data interface to retransmit the second data signals, the first data signals and the second data signals being transmitted from different devices.

### Claim 16 (depends on 15)

The DRAM memory device of claim 15, wherein whether the second unidirectional data interface retransmits the first data signals is determined by a second data (DQ) interface mode.

### Claim 17

A method of operating a DRAM memory device, comprising:
receiving configuration information;
based on the configuration information, selecting one of a first data interface mode and a second data interface mode;
based on the configuration information, selecting one of a first command/address (CA) interface mode and a second CA interface mode;
if the first data interface mode is selected, retransmitting data received via a first data interface from a second data interface;
if the second data interface mode is selected, not retransmitting data received via the first data interface from the second data interface;
if the first CA interface mode is selected, retransmitting CA signal received via a first CA interface from a second CA interface; and,
if the second CA interface mode is selected, not retransmitting data received via the first CA interface from the second CA interface.

### Claim 18 (depends on 17)

The method of claim 17, wherein the configuration information is received via connections to a substrate.

### Claim 19 (depends on 17)

The method of claim 17, wherein the configuration information is received via signals from another device.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
receiving, via a first timing interface, a timing reference signal; and,
based on a timing reference interface mode, selectively retransmitting the timing reference signal via a second timing interface.