# US 12,002,500 B2 · Writing method and erasing method of fusion memory

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- Number: US 12,002,500 B2
- Document ID: US12002500B2
- Status: Granted
- Kind: B2
- Application number: 17/426,053
- Filed: 2019-01-28
- Published: 2022-04-14
- Granted: 2024-06-04
- Earliest claimed: 2019-01-28
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Hangbing Lv; Qing Luo; Xiaoxin Xu; Tiancheng Gong; Ming Liu
- Web page: https://patentgrep.com/patent/US12002500B2

## CPC

- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G06N 3/063: using electronic means
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2297: {Power supply circuits}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

## Claims

### Claim 1

A writing method of a fusion memory, wherein the fusion memory comprises: a plurality of memory cells, and each of the plurality of memory cells comprises a bulk substrate, a source and a drain on the bulk substrate, a channel region extending between the source and the drain, a first interface layer on the channel region, a ferroelectric layer on the first interface layer, a second interface layer on the ferroelectric layer, and a gate on the second interface layer, wherein the first interface layer is configured to control a growth of a ferroelectric material of the ferroelectric layer, and the second interface layer is configured to isolate the gate and the ferroelectric layer to avoid mutual diffusion and interface damage,
the writing method comprising:
applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, wherein the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state, so as to enable the fusion memory to achieve a function of a dynamic random access memory, and
the writing method further comprising:
applying a second voltage between the gate of at least one memory cell and the bulk of at least one memory cell, wherein the second voltage is greater than the reversal voltage at which the ferroelectric layer is polarization reversed, and the source is in a grounded state, the gate is in a positive voltage state, so as to enable the fusion memory to achieve a function of a flash memory,
wherein the first voltage and the second voltage are both positive voltages.

### Claim 2 (depends on 1)

The writing method according to claim 1, wherein the first voltage is between 0.5 V and 3 V.

### Claim 3 (depends on 1)

The writing method according to claim 1, wherein the second voltage is between 3 V and 10 V.

### Claim 4 (depends on 1)

The writing method according to claim 1, wherein the applying a first voltage comprises:
applying a forward first voltage to the gate so that a voltage of the bulk is in a grounded state.

### Claim 5 (depends on 1)

The writing method according to claim 1, wherein the applying a second voltage comprises:
applying a forward second voltage to the gate so that a voltage of the bulk is in a grounded state.

### Claim 6 (depends on 1)

The writing method according to claim 1, further comprising:
adjusting a threshold voltage of a corresponding memory cell by adjusting the first voltage and/or by changing a lattice defect of the ferroelectric layer.

### Claim 7 (depends on 1)

The writing method according to claim 1, further comprising:
adjusting a threshold voltage of a corresponding memory cell by adjusting the second voltage and/or reversing the polarization.

### Claim 8 (depends on 1)

The writing method according to claim 1, further comprising:
applying a read voltage, wherein the read voltage is an intermediate value of a threshold voltage adjustment interval.

### Claim 9 (depends on 1)

A processing method of a fusion memory, comprising the writing method according to claim 1.

### Claim 10

An erasing method of a fusion memory, wherein the fusion memory comprises: a plurality of memory cells, each of the plurality of memory cells comprises a bulk substrate, a source and a drain on the bulk substrate, a channel region extending between the source and the drain, a first interface layer on the channel region, a ferroelectric layer on the first interface layer, a second interface layer on the ferroelectric layer, and a gate on the second interface layer, wherein the first interface layer is configured to control a growth of a ferroelectric material of the ferroelectric layer, and the second interface layer is configured to isolate the gate and the ferroelectric layer to avoid mutual diffusion and interface damage,
the erasing method comprising:
applying a third voltage between the gate of at least one memory cell and the bulk of at least one memory cell, wherein an absolute value of the third voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and
each of the source and the drain is grounded or in a floating state, so as to enable the fusion memory to achieve a function of a dynamic random access memory, and
the erasing method further comprising:
applying a fourth voltage between the gate of at least one memory cell and the bulk substrate of at least one memory cell, wherein an absolute value of the fourth voltage is greater than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the gate is in grounded or in the floating state, so as to enable the fusion memory to achieve a function of a flash memory,
wherein the third voltage and the fourth voltage are both negative voltages.

### Claim 11 (depends on 10)

The erasing method according to claim 10, wherein the third voltage is between −1 V and −3 V.

### Claim 12 (depends on 10)

The erasing method according to claim 10, wherein the fourth voltage is between −3 V and −10 V.

### Claim 13 (depends on 10)

The erasing method according to claim 10, wherein the applying a third voltage comprises:
applying a reverse voltage to the gate so that a voltage of the bulk is in a grounded state.

### Claim 14 (depends on 10)

The erasing method according to claim 10, wherein the applying a fourth voltage comprises:
applying a reverse voltage to the gate so that a voltage of the bulk is in a grounded state.

### Claim 15 (depends on 10)

A processing method of a fusion memory, comprising the erasing method according to claim 10.