# US 12,002,498 B2 · Coaxial top MRAM electrode > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,498 B2 - Document ID: US12002498B2 - Status: Granted - Kind: B2 - Application number: 17/806,790 - Filed: 2022-06-14 - Published: 2023-12-14 - Granted: 2024-06-04 - Earliest claimed: 2022-06-14 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Oscar van der Straten; Koichi Motoyama; Chih-Chao Yang - Web page: https://patentgrep.com/patent/US12002498B2 ## CPC - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices - H10N 50/01: Manufacture or treatment - H10N 50/10: Magnetoresistive devices - H10N 50/80: Constructional details - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter. ## Claims ### Claim 1 A semiconductor structure, comprising: a first magneto-resistive random access memory (MRAM) pillar, comprising: a bottom electrode layer; a reference layer connected above the bottom electrode layer; a free layer; and a tunnel barrier between the reference layer and the free layer, wherein the MRAM pillar comprises a pillar diameter; and a coaxial top electrode comprising a top diameter that is less than the pillar diameter wherein the coaxial top electrode comprises an inner conductor core and an outer metal barrier shell. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, further comprising: a second MRAM pillar adjacent to the first MRAM pillar; and an inter-level dielectric (ILD) between the first MRAM pillar and the second MRAM pillar. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, further comprising a bottom metal wire directly connected to the bottom electrode layer, wherein the bottom metal wire comprises a first metal level of a back-end-of-line (BEOL) network. ### Claim 4 (depends on 3) The semiconductor structure of claim 3, further comprising a top metal wire directly connected to the coaxial top electrode, wherein the top metal wire comprises a second metal level of the BEOL network. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, wherein the outer metal barrier shell comprises a metal material that is the same as at least a portion of the top metal wire. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein the coaxial top electrode comprises an inner conductor core and an outer nucleation layer shell. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, further comprising a metal sealing layer between the free layer and the coaxial top electrode. ### Claim 8 A method of fabricating a magneto-resistive random access memory (MRAM) device, comprising: forming a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer; forming a first coaxial top electrode surrounded by a first conformal dielectric, wherein the coaxial top electrode comprises a top diameter and the conformal dielectric comprises a pillar diameter; etching the bottom electrode layer, the reference layer, the free layer, and the tunnel barrier to form an MRAM pillar, wherein the first conformal dielectric masks the bottom electrode layer, the reference layer, the free layer, and the tunnel barrier; removing the conformal dielectric; and forming an inter-level dielectric (ILD) around the MRAM pillar and the top electrode. ### Claim 9 (depends on 8) The method of claim 8, comprising: forming a second MRAM pillar by etching the bottom electrode layer, the reference layer, the free layer, and the tunnel barrier below a second top electrode surrounded by a second conformal dielectric. ### Claim 10 (depends on 8) The method of claim 8, further comprising forming a bottom metal wire directly connected to the bottom electrode layer, wherein the bottom metal wire comprises a first metal level of a back-end-of-line (BEOL) network. ### Claim 11 (depends on 10) The method of claim 10, further comprising forming a top metal wire directly connected to the coaxial top electrode, wherein the top metal wire comprises a second metal level of the BEOL network. ### Claim 12 (depends on 11) The method of claim 11, further comprising forming an outer metal barrier shell around the first top electrode, wherein the outer metal barrier shell comprises a metal material that is the same as at least a portion of the top metal wire. ### Claim 13 (depends on 8) The method of claim 8, further comprising forming an outer nucleation layer shell around an inner conductor core of the first coaxial top electrode. ### Claim 14 (depends on 13) The method of claim 13, further comprising forming a metal sealing layer between the free layer and the first coaxial top electrode. ### Claim 15 (depends on 8) The method of claim 8, wherein forming the ILD comprises a selection from the group consisting of: spin-on deposition, chemical-vapor deposition (CVD), and plasma-enhanced chemical vapor deposition (PECVD). ### Claim 16 A semiconductor structure, comprising: a first magneto-resistive random access memory (MRAM) pillar comprising: a first body comprising a first pillar diameter; and a first coaxial top electrode comprising a first top diameter that is smaller than the first pillar diameter, wherein the first coaxial top electrode comprises an inner conductor core and an outer metal barrier shell; a second MRAM pillar adjacent to the first MRAM pillar comprising: a second body comprising a second pillar diameter; and a second coaxial top electrode comprising a second top diameter that is smaller than the second pillar diameter; and an inter-level dielectric (ILD) between the first MRAM pillar and the second MRAM pillar. ### Claim 17 (depends on 16) The semiconductor structure of claim 16, wherein a top distance between the first coaxial top electrode and the second coaxial top electrode is greater than a body distance between the first body and the second body. ### Claim 18 (depends on 16) The semiconductor structure of claim 16, further comprising a bottom metal wire directly connected to the first body, wherein the bottom metal wire comprises a first metal level of a back-end-of-line (BEOL) network. ### Claim 19 (depends on 18) The semiconductor structure of claim 18, further comprising a metal sealing layer between the first body and the first coaxial top electrode. ### Claim 20 (depends on 18) The semiconductor structure of claim 18, wherein the first coaxial top electrode comprises an outer nucleation layer shell.