# US 12,002,482 B2 · Data transfer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,482 B2 - Document ID: US12002482B2 - Status: Granted - Kind: B2 - Application number: 17/845,703 - Filed: 2022-06-21 - Published: 2022-12-01 - Granted: 2024-06-04 - Earliest claimed: 2011-12-14 - Assignees: Cirrus Logic, Inc. - Applicants: Cirrus Logic International Semiconductor Ltd. - Inventors: John Paul Lesso; Peter John Frith; John Laurence Pennock - Web page: https://patentgrep.com/patent/US12002482B2 ## CPC - G10L 19/167: {Audio streaming, i.e. formatting and decoding of an encoded audio signal representation into a data stream for transmission or storage purposes} - G06F 3/162: {Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs} - G10L 19/002: Dynamic bit allocation (for perceptual audio coders G10L19/032) - G10L 19/008: Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing - H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} - H04L 25/4902: {Pulse width modulation; Pulse position modulation} - H04L 25/4904: {using self-synchronising codes, e.g. split-phase codes} - G10L: SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream. ## Claims ### Claim 1 Digital data transmission circuitry comprising: interface circuitry configured to receive an input signal comprising a plurality of data pulses representative of input data and to transmit the data pulses over a first communications link; wherein the interface circuitry comprises: pulse-length modulator circuitry configured to receive the input signal and to generate a plurality of data pulses representative of the input data; and at least two data inputs for receiving respective input digital data streams of data bits, wherein the pulse-length modulator circuitry is configured to generate a single data pulse having a rising edge and a falling edge within each of a plurality of transfer periods defined by a first clock signal, responsive to said input digital data streams and to said first clock signal; wherein the time of occurrence of the rising edge and the falling edge of the data pulse encodes the then current data bits of said input digital data streams. ### Claim 2 (depends on 1) Digital data transmission circuitry according to claim 1, wherein said input data comprises audio data. ### Claim 3 (depends on 1) Digital data transmission circuitry according to claim 1, wherein said first communications link comprises a single link. ### Claim 4 (depends on 3) Digital data transmission circuitry according to claim 3, wherein said single link comprises a single wire or a single bus. ### Claim 5 (depends on 3) Digital data transmission circuitry according to claim 3, wherein said single link comprises a single pole or pin of a plug-socket connection that is used to couple a host device that includes the digital data transmission circuitry to an accessory device that is external to the host device. ### Claim 6 (depends on 5) Digital data transmission circuitry according to claim 5, wherein said plug-socket connection comprises a three- or four-pole jack plug or socket. ### Claim 7 (depends on 3) Digital data transmission circuitry according to claim 3, wherein said single link comprises a single path on a printed circuit board that is connected to a pin of a digital signal processor or codec of the digital data transmission circuitry. ### Claim 8 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the interface circuitry is bi-directional, and wherein the pulse-length modulator circuitry is configured to transmit data pulses during a first transfer period and the interface circuitry is configured to receive data pulses during a second, different transfer period. ### Claim 9 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the interface circuitry is bi-directional and comprises a drive circuit for voltage modulating the first communications link based on the data pulses and a read circuit responsive to the resultant voltage on the first communications link, wherein the read circuit is configured to subtract the drive voltage modulation from the resultant voltage signal. ### Claim 10 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the occurrence said rising and falling edges of the data pulse are quantised in time within the transfer period. ### Claim 11 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein said input digital data streams comprises at least two audio data streams. ### Claim 12 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein said input digital data streams comprises at least one stream of control data for controlling the operation of a receiver of the least two audio data streams. ### Claim 13 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the rising and falling edges of each data pulse are synchronised to a second clock signal, where the second clock signal has a frequency greater than the first clock signal. ### Claim 14 (depends on 13) Digital data transmission circuitry as claimed in claim 13, wherein the second clock signal frequency is a multiple of the first clock signal frequency. ### Claim 15 (depends on 13) Digital data transmission circuitry as claimed in claim 13, wherein the first clock frequency is equal to the sample rate of said at least one digital data stream. ### Claim 16 (depends on 15) Digital data transmission circuitry as claimed in claim 15, wherein the sample rate of said at least one digital stream is a multiple of a standard audio frequency sample rate. ### Claim 17 (depends on 13) Digital data transmission circuitry as claimed in claim 13, wherein the pulse-length modulator circuitry is configured such that there is at least one period defined by the second clock signal at the start of the transfer period before the start of a data pulse. ### Claim 18 (depends on 13) Digital data transmission circuitry as claimed in claim 13, wherein the pulse-length modulator circuitry is configured such that there is at least one period defined by the second clock signal at the end of a data pulse before the end of the transfer period. ### Claim 19 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the pulse-length modulator circuitry is configured such that at least one possible combination of input data can be encoded by more than one possible data pulses. ### Claim 20 (depends on 19) Digital data transmission circuitry as claimed in claim 19, wherein the pulse-length modulator circuitry is configured such that, over time, different instances of said combination of input data is encoded by different ones of said possible data pulses. ### Claim 21 (depends on 20) Digital data transmission circuitry as claimed in claim 20, wherein said possible data pulses for encoding a given combination of input data have different durations and the pulse-length modulator circuitry is configured to select between the possible data pulses so as to minimise any d.c. imbalance over time in the transmitted data pulses. ### Claim 22 (depends on 20) Digital data transmission circuitry as claimed in claim 20, wherein one of said possible data pulses for encoding a given combination of input data has a duration of greater than half the transfer period and another of said possible pulses has a duration of less than half the transfer period. ### Claim 23 (depends on 1) Digital data transmission circuitry as claimed in claim 1, wherein the pulse-length modulator circuitry is configured such that there is at least one possible data pulse that is not used to encode the input data but which may be transmitted by the pulse-length modulator circuitry for synchronisation and/or control.