# US 12,002,429 B2 · Display panel and display apparatus including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,429 B2 - Document ID: US12002429B2 - Status: Granted - Kind: B2 - Application number: 18/211,322 - Filed: 2023-06-19 - Published: 2023-10-19 - Granted: 2024-06-04 - Earliest claimed: 2020-01-20 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Gyungsoon Park; Gunhee Kim; Hyeongseok Kim; Youngwan Seo; Chongchul Chai - Web page: https://patentgrep.com/patent/US12002429B2 ## CPC - G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)} - G09G 3/3275: Details of drivers for data electrodes - H10K 59/12: Active-matrix OLED [AMOLED] displays - H10K 59/121: characterised by the geometry or disposition of pixel elements - H10K 59/124: Insulating layers formed between TFT elements and OLED elements - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10K 59/353: {characterised by the geometrical arrangement of the RGB subpixels} - H10K 77/00: Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80 - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/061: for resetting or blanking - H10K 59/65: OLEDs integrated with inorganic image sensors - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A display panel includes a 1-1st sub-pixel and a 1-2nd sub-pixel disposed in a first row, a 2-1st sub-pixel disposed in a second row and a 3-1st sub-pixel and a 3-2nd sub-pixel disposed in a third row. A first data line extends from the first row to the third row and electrically connects a pixel circuit of the 1-1st sub-pixel, a pixel circuit of the 2-1st sub-pixel, and a pixel circuit of the 3-1st sub-pixel. A 2-1st data line is electrically connected to a pixel circuit of the 1-2nd sub-pixel. A 2-2nd data line is electrically connected to a pixel circuit of the 3-2nd sub-pixel. A first bridge line is disposed on a different layer than the data lines and contacts the 2-1st data line and the 2-2nd data line and includes an overlapping portion extending along at least a portion of the first data line. ## Claims ### Claim 1 A display panel comprising: a 1-1st sub-pixel and a 1-2nd sub-pixel disposed over a substrate to be in a main display area, the main display area outside a component area in a plan view; a 2-1st sub-pixel and a 2-2nd sub-pixel disposed over the substrate to be in the component area, the 2-1st sub-pixel and the 2-2nd sub-pixel including thin-film transistors, each of the thin-film transistors having a semiconductor layer; and a conductive layer disposed between the semiconductor layer and the substrate, the conductive layer including an opening having a polygonal shape in the component area in the plan view, at least one internal angle of the opening being an obtuse angle. ### Claim 2 (depends on 1) The display panel of claim 1, wherein the conductive layer overlaps the thin-film transistors of the 2-1st sub-pixel and the 2-2nd sub-pixel in the plan view. ### Claim 3 (depends on 1) The display panel of claim 1, wherein the conductive layer overlaps all thin-film transistors that the 2-1st sub-pixel and the 2-2nd sub-pixel include, in the plan view. ### Claim 4 (depends on 1) The display panel of claim 1, wherein the conductive layer overlaps pixel electrodes that the 2-1st sub-pixel and the 2-2nd sub-pixel include, in the plan view. ### Claim 5 (depends on 1) The display panel of claim 1, further comprising a metal layer disposed between the substrate and a thin-film transistor that the 1-1st sub-pixel includes. ### Claim 6 (depends on 5) The display panel of claim 5, wherein the metal layer overlaps a part of a semiconductor layer of the thin-film transistor of the 1-1st sub-pixel, the part of the semiconductor layer overlapping a gate electrode of the thin-film transistor of the 1-1st sub-pixel. ### Claim 7 (depends on 5) The display panel of claim 5, wherein the conductive layer disposed on a same layer on which the metal layer is disposed. ### Claim 8 (depends on 1) The display panel of claim 1, wherein the opening of the conductive layer defines a transmission area in the component area. ### Claim 9 (depends on 8) The display panel of claim 8, a light-transmittance in the component area is different from a light-transmittance in the main display area. ### Claim 10 (depends on 8) The display panel of claim 8, further comprising an organic insulating layer disposed between the substrate and pixel electrodes that the 2-1st sub-pixel and the 2-2nd sub-pixel include, the organic insulating layer includes a hole corresponding to the opening of the conductive layer. ### Claim 11 (depends on 10) The display panel of claim 10, the hole of the organic insulating layer overlaps the opening of the conductive layer in the plan view. ### Claim 12 (depends on 1) The display panel of claim 1, wherein a group including the 1-1st sub-pixel and the 1-2nd sub-pixel repeatedly appears in the main display area and a group including the 2-1st sub-pixel and the 2-2nd sub-pixel repeatedly appears in the component area. ### Claim 13 (depends on 12) The display panel of claim 12, wherein the group including the 2-1st sub-pixel and the 2-2nd sub-pixel is disposed over the conductive layer. ### Claim 14 (depends on 12) The display panel of claim 12, wherein the group including the 2-1st sub-pixel and the 2-2nd sub-pixel overlaps the conductive layer in the plan view. ### Claim 15 (depends on 1) The display panel of claim 1, wherein the opening of the conductive layer has a shape of an octagon. ### Claim 16 (depends on 1) The display panel of claim 1, further comprising a bridge line transferring a signal to a sub-pixel in the main display area arranged next to the component area. ### Claim 17 (depends on 1) The display panel of claim 1, wherein the bridge line overlaps the conductive layer in the component area in the plan view. ### Claim 18 (depends on 1) The display panel of claim 1, further comprising a driving voltage line in the main display area, the driving voltage line being electrically connected to the 1-1st sub-pixel to apply a driving voltage thereto, wherein the conductive layer is electrically connected to the driving voltage line. ### Claim 19 (depends on 18) The display panel of claim 18, wherein the driving voltage line is disposed on a layer which is different from a layer on which the conductive layer is disposed. ### Claim 20 (depends on 1) The display panel of claim 1, wherein the component area has a shape of a circle in the plan view. ### Claim 21 A display panel comprising: a 1-1st sub-pixel and a 1-2nd sub-pixel disposed over a substrate to be in a main display area, the main display area outside a component area in a plan view; a 2-1st sub-pixel and a 2-2nd sub-pixel disposed over the substrate to be in the component area, the 2-1st sub-pixel and the 2-2nd sub-pixel including thin-film transistors, each of the thin-film transistors having a semiconductor layer; and a conductive layer disposed between the semiconductor layer and the substrate, the conductive layer including an opening having a polygonal shape in the component area in the plan view, the conductive layer overlapping the thin-film transistors of the 2-1st sub-pixel and the 2-2nd sub-pixel in the plan view.