# US 12,002,428 B2 · Gate driving circuit having a node controller and display device thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,428 B2 - Document ID: US12002428B2 - Status: Granted - Kind: B2 - Application number: 17/962,042 - Filed: 2022-10-07 - Published: 2023-06-29 - Granted: 2024-06-04 - Earliest claimed: 2021-12-29 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Jae Sung Park; Yong Ho Kim - Web page: https://patentgrep.com/patent/US12002428B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3275: Details of drivers for data electrodes - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2320/0252: Improving the response speed - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A gate driving circuit that can be stably driven by improving output characteristics of a last output buffer unit, and a display device comprising the gate driving circuit, are discussed. The gate driving circuit can include a plurality of subordinately connected stages, where an Nth (N being a natural number) stage includes a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal. The Nth stage can further include a plurality of scan pulse output units configured to receive a plurality of scan clocks, and output each of the scan clocks as a scan pulse according to voltages of the first node and the second node. ## Claims ### Claim 1 A gate driving circuit comprising a plurality of subordinately connected stages, wherein an Nth stage, N being a natural number, includes: a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal; and a plurality of scan pulse output units configured to receive a plurality of scan clocks, and output each of the scan clocks as a scan pulse according to the voltages of the first node and the second node, wherein a last scan pulse output unit among the plurality of scan pulse output units further outputs a corresponding scan clock as a scan pulse while receiving a first node voltage of an (N+1)th stage, wherein the last scan pulse output unit includes: a first pull-up transistor turned on or turned off according to a voltage of the first node to output a corresponding scan clock to an output terminal; and a second pull-up transistor turned on or turned off according to the first node voltage of the (N+1)th stage to output the corresponding scan clock to an output terminal, and wherein the first pull-up transistor and the second pull-up transistor are connected in parallel. ### Claim 2 (depends on 1) The gate driving circuit according to claim 1, further comprising a carry signal output unit configured to output a carry clock as a carry pulse according to the voltages of the first node and the second node. ### Claim 3 (depends on 1) The gate driving circuit according to claim 1, wherein the last scan pulse output unit further includes: a pull-down transistor turned on or turned off according to a voltage of the second node to output low-voltage power to an output terminal. ### Claim 4 (depends on 1) The gate driving circuit according to claim 1, wherein the last scan pulse output unit further includes a capacitor connected between a gate electrode of the first pull-up transistor and an output terminal to bootstrap the first node. ### Claim 5 (depends on 1) The gate driving circuit according to claim 1, wherein at least a portion of the scan pulse for the corresponding scan clock output by the last scan pulse output unit overlaps with a peak voltage level of the first node voltage of the (N+1)th stage. ### Claim 6 (depends on 1) The gate driving circuit according to claim 1, wherein each of the first node voltage of the Nth stage and the first node voltage of the (N+1)th stage increases in a stepwise manner and then decreases in a stepwise manner. ### Claim 7 (depends on 6) The gate driving circuit according to claim 6, wherein a peak voltage level of the first node voltage of the Nth stage occurs before a peak voltage level of the first node voltage of the (N+1)th stage. ### Claim 8 (depends on 7) The gate driving circuit according to claim 7, wherein the peak voltage level of the first node voltage of the (N+1)th stage corresponds to a rising edge of the scan pulse for the corresponding scan clock output by the last scan pulse output unit. ### Claim 9 (depends on 6) The gate driving circuit according to claim 6, wherein a falling edge of the scan pulse for the corresponding scan clock output by the last scan pulse output unit correspond to a falling edge of the first node voltage of the Nth stage. ### Claim 10 (depends on 1) The gate driving circuit according to claim 1, wherein a timing of a falling edge of the scan pulse for the corresponding scan clock output by the last scan pulse output unit depends on the first node voltage of the (N+1)th stage. ### Claim 11 A display device comprising: a display panel including data lines, gate lines, and subpixels; a data driving circuit configured to supply a data signal of an input image to the data lines; and a gate driving circuit configured to supply a gate signal to the gate lines, wherein: the gate driving circuit includes a plurality of subordinately connected stages, an Nth stage, N being a natural number, includes: a node controller configured to control voltages of a first node and a second node according to a set signal and a reset signal; and a plurality of scan pulse output units configured to receive a plurality of scan clocks, and output each of the scan clocks as a scan pulse according to voltages of the first node and the second node, wherein a last scan pulse output unit among the plurality of scan pulse output units further outputs a corresponding scan clock as a scan pulse while receiving a first node voltage of an (N+1)th stage, wherein the last scan pulse output unit includes: a first pull-up transistor configured to turn on or off based on a voltage of the first node to output a corresponding scan clock to an output terminal; and a second pull-up transistor configured to turn on or off based on the first node voltage of the (N+1)th stage to output the corresponding scan clock to an output terminal, and wherein the first pull-up transistor and the second pull-up transistor are connected in parallel. ### Claim 12 (depends on 11) The display device according to claim 11, further comprising a carry signal output unit configured to output a carry clock as a carry pulse based on the voltages of the first node and the second node. ### Claim 13 (depends on 11) The display device according to claim 11, wherein the last scan pulse output unit further includes: a pull-down transistor configured to turn on or off based on a voltage of the second node to output low-voltage power to an output terminal. ### Claim 14 (depends on 11) The display device according to claim 11, wherein the last scan pulse output unit further includes a capacitor connected between a gate electrode of the first pull-up transistor and an output terminal to bootstrap the first node. ### Claim 15 (depends on 11) The display device according to claim 11, wherein at least a portion of the scan pulse for the corresponding scan clock output by the last scan pulse output unit overlaps with a peak voltage level of the first node voltage of the (N+1)th stage. ### Claim 16 (depends on 11) The display device according to claim 11, wherein a timing of a falling edge of the scan pulse for the corresponding scan clock output by the last scan pulse output unit depends on the first node voltage of the (N+1)th stage.