# US 12,002,415 B2 · Display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,415 B2 - Document ID: US12002415B2 - Status: Granted - Kind: B2 - Application number: 18/187,714 - Filed: 2023-03-22 - Published: 2023-07-13 - Granted: 2024-06-04 - Earliest claimed: 2021-04-28 - Assignees: Xiamen Tianma Micro-Electronics Co., Ltd. - Applicants: Xiamen Tianma Micro-Electronics Co., Ltd. - Inventors: Jieliang Li; Ping An - Web page: https://patentgrep.com/patent/US12002415B2 ## CPC - G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED] - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0216: Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/061: for resetting or blanking - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device, and a bias adjustment device. The drive device includes a drive transistor. The data write device is configured to provide a data signal for the drive device. The bias adjustment device is configured to provide a bias adjustment signal to the drive device. The pixel circuit includes a first light-emitting control device, the first light-emitting control device is connected between a first power supply voltage signal line and the drive device, and the first power supply voltage signal line is configured to provide a high-level signal, or, the pixel circuit includes an initialization device, the initialization device is connected between an initialization signal line and the light-emitting element, and the initialization signal line is configured to provide a low-level signal. ## Claims ### Claim 1 A display panel, comprising: a pixel circuit and a light-emitting element; wherein the pixel circuit comprises a data write device, a drive device, and a bias adjustment device; the drive device comprises a drive transistor; the data write device is configured to provide a data signal for the drive device; the bias adjustment device is configured to provide a bias adjustment signal to the drive device; and wherein the pixel circuit comprises a first light-emitting control device, the first light-emitting control device is connected between a first power supply voltage signal line and the drive device, and the first power supply voltage signal line is configured to provide a high-level signal, and the drive transistor is a P-type transistor, the bias adjustment signal is V0, and the high-level signal provided by the first power supply voltage signal line is Vdd; and V0Vdd×1.2; or wherein the pixel circuit comprises an initialization device, the initialization device is connected between an initialization signal line and the light-emitting element, and the initialization signal line is configured to provide a low-level signal, and the drive transistor is a N-type transistor, the bias adjustment signal is V0, and the low-level signal provided by the initialization signal line is Vini; and V0Vini×1.2. ### Claim 2 (depends on 1) The display panel according to claim 1, wherein in a case where the drive transistor is the P-type transistor, V05.5 V; or, in a case where the drive transistor is the N-type transistor, V0−4.3 V. ### Claim 3 (depends on 1) The display panel according to claim 1, wherein in a case where the drive transistor is the P-type transistor, a value range of V0 is from 6 V to 10 V; or, in a case where the drive transistor is the N-type transistor, a value range of V0 is from −10 V to −5V. ### Claim 4 (depends on 1) The display panel according to claim 1, wherein a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on and the bias adjustment device is configured to receive the bias adjustment signal. ### Claim 5 (depends on 1) The display panel according to claim 1, wherein the data write device is connected to a source of the drive transistor; and the bias adjustment device is connected between a source of the drive transistor or a drain of the drive transistor and a bias adjustment signal line. ### Claim 6 (depends on 1) The display panel according to claim 1, wherein the pixel circuit further comprises a compensation device, and the compensation device is connected between a gate of the drive transistor and a drain of the drive transistor; a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on and the compensation device is turned off. ### Claim 7 (depends on 1) The display panel according to claim 1, wherein the pixel circuit further comprises a reset device; an end of the reset device is connected to a reset signal line and configured to receive a reset signal, and another end of the reset device is connected to a gate of the drive transistor; and in a reset stage, the reset device is turned on to provide the reset signal to the gate of the drive transistor. ### Claim 8 (depends on 7) The display panel according to claim 7, wherein a working process of the pixel circuit comprises a bias adjustment stage, and in the bias adjustment stage, the bias adjustment device is turned on; and the reset stage at least partially overlap the bias adjustment stage in time. ### Claim 9 (depends on 1) The display panel according to claim 1, wherein the pixel circuit further comprises a reset device; an end of the reset device is connected to a reset signal line and configured to receive a reset signal, and another end of the reset device is connected to a drain of the drive transistor; the pixel circuit further comprises a compensation device, the compensation device is connected between a gate of the drive transistor and the drain of the drive transistor; and in a reset stage, the reset device and the compensation device are turned on to provide the reset signal to a gate of the drive transistor. ### Claim 10 (depends on 1) The display panel according to claim 1, wherein in an initialization stage, the initialization device is turned on to provide an initialization signal to the light-emitting element. ### Claim 11 (depends on 10) The display panel according to claim 10, wherein a control terminal of the initialization device and a control terminal of the bias adjustment device are connected to a same scan signal line, and in the initialization stage, the scan signal line is configured to control the initialization device and the bias adjustment device to be turned on at a same time. ### Claim 12 (depends on 10) The display panel according to claim 10, wherein the pixel circuit further comprises a reset device; an end of the reset device is connected to a reset signal line and configured to receive a reset signal, another end of the reset device is connected to a gate of a drive transistor, and in a reset stage, the reset device is turned on to provide the reset signal to a gate of the drive transistor, wherein a control terminal of the initialization device, a control terminal of the bias adjustment device, and a control terminal of the reset device are all connected to a same scan signal line, and in the initialization stage, the scan signal line is used to control the initialization device, the bias adjustment device, and the reset device to be turned on at a same time. ### Claim 13 (depends on 1) The display panel according to claim 1, wherein a working process of the pixel circuit comprises a light-emission stage and a bias adjustment stage; wherein in the light emission stage, the source voltage of the drive transistor is Vs1, the voltage of the drain of the drive transistor is Vd1, and the voltage of the gate of the drive transistor is Vg1; in the bias adjustment stage, the source voltage of the drive transistor is Vs2, the voltage of the drain of the drive transistor is Vd2, the voltage of the gate of the drive transistor is Vg2, and the bias adjustment signal is V0; in a case where the drive transistor is a P-type transistor, (V0−Vg2)(Vg1−Vd1); or, in a case where the drive transistor is an N-type transistor, (Vg2−V0)(Vd1−Vg1). ### Claim 14 (depends on 1) The display panel according to claim 1, wherein in a case where the drive transistor is the P-type transistor, the data write device and the first light-emitting control device are connected to a source of the drive transistor; or, in a case where the drive transistor is the N-type transistor, the data write device is connected to a source of the drive transistor, and the first light-emitting control device is connected to a drain of the drive transistor. ### Claim 15 (depends on 1) The display panel according to claim 1, wherein the display panel comprises a bias adjustment signal line, and a width of the bias adjustment signal line is lower than a width of the first power supply voltage signal line. ### Claim 16 (depends on 1) The display panel according to claim 1, wherein the display panel comprises a bias adjustment signal line; and the bias adjustment signal line and the first power supply voltage signal line are disposed in a same layer; or, the bias adjustment signal line and the first power supply voltage signal line are disposed in different layers. ### Claim 17 (depends on 1) The display panel according to claim 1, wherein the display panel comprises a bias adjustment signal line; and the bias adjustment signal line and the first power supply voltage signal line extend in a same direction; or, the bias adjustment signal line and the initialization signal line extend in a same direction. ### Claim 18 (depends on 1) The display panel according to claim 1, wherein the display panel comprises a bias adjustment signal line; and the display panel comprises a side frame of long sides and a side frame of short sides; and an extension direction of the bias adjustment signal line is parallel to an extension direction of the side frame of short sides of the display panel. ### Claim 19 (depends on 1) The display panel according to claim 1, wherein the display panel comprises a bias adjustment signal line; and the bias adjustment signal bus is disposed in two or more side frames of the display panel. ### Claim 20 A display device, comprising a display panel, wherein the display panel, comprises: a pixel circuit and a light-emitting element; wherein the pixel circuit comprises a data write device, a drive device, and a bias adjustment device; the drive device comprises a drive transistor; the data write device is configured to provide a data signal for the drive device; the bias adjustment device is configured to provide a bias adjustment signal to the drive device; and wherein the pixel circuit comprises a first light-emitting control device, the first light-emitting control device is connected between a first power supply voltage signal line and the drive device, and the first power supply voltage signal line is configured to provide a high-level signal, and the drive transistor is a P-type transistor, the bias adjustment signal is V0, and the high-level signal provided by the first power supply voltage signal line is Vdd; and V0Vdd×1.2; or, wherein the pixel circuit comprises an initialization device, the initialization device is connected between an initialization signal line and the light-emitting element, and the initialization signal line is configured to provide a low-level signal, and the drive transistor is an N-type transistor, the bias adjustment signal is V0, and the low-level signal provided by the initialization signal line is Vini; and V0Vini×1.2.