# US 12,002,410 B2 · Array substrate and detection method therefor, and tiled display panel

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- Number: US 12,002,410 B2
- Document ID: US12002410B2
- Status: Granted
- Kind: B2
- Application number: 17/642,025
- Filed: 2021-04-08
- Published: 2022-12-22
- Granted: 2024-06-04
- Earliest claimed: 2020-05-13
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: BOE Technology Group Co., Ltd.
- Inventors: Hao Chen; Zhenyu Zhang; Jiao Zhao; Li Xiao; Dongni Liu; Haoliang Zheng; Liang Chen; Minghua Xuan; Ming Yang; Xinhong Lu; Qi Qi
- Web page: https://patentgrep.com/patent/US12002410B2

## CPC

- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G01R 31/52: Testing for short-circuits, leakage current or ground faults
- G01R 31/54: Testing for continuity
- G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)}
- G09G 3/035: {for flexible display surfaces}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 86/60: wherein the TFTs are in active matrices
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W 90/00: Package configurations
- G09F 9/3026: {Video wall, i.e. stackable semiconductor matrix display modules (video wall control systems G06F3/1446, G09G2300/026)}
- G09F 9/33: being semiconductor devices, e.g. diodes
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G 2330/021: Power management, e.g. power saving
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS

## Abstract

An array substrate, a detection method for the array substrate, and a tiled display panel. In the array substrate, each of pixels (1) comprises sub-pixels (01) of at least three colors and a pixel driving chip (02) for driving each sub-pixel (01) to emit light; each sub-pixel (01) comprises at least one inorganic light-emitting diode; a display area (A1) further comprises: a positive signal line (Hm) connected to a positive electrode of each inorganic light-emitting diode, and a data signal line (Dm), a scanning line (Sn), and a reference signal line (Vm) connected to each pixel driving chip (02); each pixel driving chip (02) is used for writing signals of the data signal line (Dm) into the sub-pixels (01) of different colors under the control of the corresponding scanning line (Sn) in a time division manner.

## Claims

### Claim 1

An array substrate, comprising:
a display region, provided with a plurality of scanning lines, a plurality of data signal lines, a plurality of positive signal lines and a plurality of reference signal lines, and a plurality of pixels arranged in an array mode; and
a bezel region; wherein
at least one of the plurality of pixels comprises: sub-pixels of at least three colors and a pixel driving chip driving each of the sub-pixels to emit light;
each of the sub-pixels comprises at least one inorganic light-emitting diode;
the pixel driving chip is connected with a positive electrode of the inorganic light-emitting diode in each of the sub-pixels it drives, at least one of the plurality of data signal lines, at least one of the plurality of scanning lines and at least one of the plurality of reference signal lines; and
the pixel driving chip is configured to write a signal of the data signal line into the sub-pixels of different colors under control of the scanning line, corresponding to the pixel driving chip, in a time division, wherein the reference signal line is configured to provide a negative signal for the pixel driving chip so as to form a current path between the inorganic light-emitting diode and the pixel driving chip;
wherein the plurality of pixels comprise N pixel rows arranged in a first direction and M pixel columns arranged in a second direction, wherein N and M are both integers larger than 1;
the plurality of scanning lines extend in the first direction and are arranged in the second direction, the plurality of data signal lines extend in the second direction and are arranged in the first direction, the plurality of positive signal lines extend in the second direction and are arranged in the first direction, and the plurality of reference signal lines extend in the second direction and are arranged in the first direction; and
the first direction is different from the second direction;
wherein each of the pixels comprises: a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;
each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines and two of the plurality of positive signal lines; and
one of the two positive signal lines is connected with a positive electrode of an inorganic light-emitting diode in the first color sub-pixel, and the other of the two positive signal lines is connected with positive electrodes of inorganic light-emitting diodes in the third color sub-pixel and the second color sub-pixel;
wherein the display region further comprises scanning signal routing wires connected with the plurality of scanning lines in a one-to-one correspondence, and the scanning signal routing wires extend in the second direction;
wherein the scanning lines are in a first metal layer, and the scanning signal routing wires, the data signal lines, the reference signal lines and the positive signal lines are in a second metal layer;
wherein the bezel region at one end of the data signal lines comprises a bent region, a wiring region and a bonding region sequentially far away from the display region;
at least one first chip and at least one second chip are arranged in the bonding region;
the scanning signal routing wires and the data signal lines are sequentially connected with the first chip in a bonding mode through routing wires in the bent region and the wiring region; and
the reference signal lines and the positive signal lines are sequentially connected with the second chip in a bonding mode through routing wires in the bent region and the wiring region.

### Claim 2 (depends on 1)

The array substrate according to claim 1 wherein:
each of the pixel rows corresponds to one of the plurality of scanning lines, and each of the pixel columns corresponds to one of the plurality of data signal lines, one of the plurality of reference signal lines and one of the plurality of positive signal lines.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein:
N=M, one side of each of the pixel columns is correspondingly provided with one of the scanning signal routing wires, and only one of the scanning signal routing wires is arranged between every two adjacent pixel columns.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein:
N>M, at least one of the scanning signal routing wires is arranged on each of two sides of at least one of the pixel columns; and
at least one of the scanning signal routing wires is arranged between at least part of every two adjacent pixel columns, and a quantity of the scanning signal routing wires between the two adjacent pixel columns does not exceed two.

### Claim 5 (depends on 1)

A splicing display panel, comprising a plurality of array substrates according to claim 1.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein:
N=M, one side of each of the pixel columns is correspondingly provided with one of the scanning signal routing wires, and only one of the scanning signal routing wires is arranged between every two adjacent pixel columns.

### Claim 7 (depends on 5)

The array substrate according to claim 5, wherein:
N>M, at least one of the scanning signal routing wires is arranged on each of two sides of at least one of the pixel columns; and
at least one of the scanning signal routing wires is arranged between at least part of every two adjacent pixel columns, and a quantity of the scanning signal routing wires between the two adjacent pixel columns does not exceed two.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein:
a plurality of first chips and a plurality of second chips are arranged in the bonding region; and
the first chips and the second chips are distributed in the bonding region at intervals.

### Claim 9 (depends on 1)

The array substrate according to claim 1, wherein:
the routing wires in the bent region are all in the second metal layer.

### Claim 10 (depends on 1)

The array substrate according to claim 1, wherein:
in the wiring region, the routing wires connected with the scanning signal routing wires and the routing wires connected with the data signal lines are all in the first metal layer; and
in the wiring region, the routing wires connected with the reference signal lines and the routing wires connected with the positive signal lines are all in the second metal layer.

### Claim 11 (depends on 1)

The array substrate according to claim 1 wherein:
in the wiring region, the routing wires connected with the scanning signal routing wires and connected with the data signal lines are all in the second metal layer; and
in the wiring region, the routing wires connected with the reference signal lines and connected with the positive signal lines are all in the first metal layer.

### Claim 12 (depends on 1)

The array substrate according to claim 1, wherein:
the scanning signal routing wires, the data signal lines, the reference signal lines and the positive signal lines are all longitudinal signal lines;
the bezel region further comprises: a first signal input region on one side of the bonding region far away from the wiring region and a second signal input region at one end of the data signal lines far away from the bent region;
first input electrodes in one-to-one correspondence with the longitudinal signal lines are arranged in the first signal input region, and the respective longitudinal signal lines in the display region are connected with the respective first input electrodes sequentially through the routing wires in the bent region and the wiring region; and
second input electrodes in one-to-one correspondence connection with the longitudinal signal lines are arranged in the second signal input region.

### Claim 13 (depends on 12)

The array substrate according to claim 12, wherein:
the bezel region at one end of the scanning lines comprises a third signal input region;
the bezel region at another end of the scanning lines comprises a fourth signal input region;
third input electrodes in one-to-one correspondence connection with the scanning lines are arranged in the third signal input region; and
fourth input electrodes in one-to-one correspondence connection with the scanning lines are arranged in the fourth signal input region.

### Claim 14 (depends on 12)

A method for detecting the array substrate according to claim 12, wherein the longitudinal signal lines and the scanning lines in the display region are all to-be-detected lines, and the method comprises:
inputting, for each of the to-be-detected lines, a test signal into one input electrode connected with a to-be-detected line;
detecting whether another input electrode connected with the to-be-detected line outputs a signal, and in response to that the another input electrode connected with the to-be-detected line does not output the signal, determining that the to-be-detected line is disconnected; and
detecting whether an input electrode of another to-be-detected line except the to-be-detected line input with the test signal outputs a signal, and in response to that the input electrode of the another to-be-detected line outputs the signal, determining that a short circuit occurs between the to-be-detected line input with the test signal and the another to-be-detected line the input electrode of which outputs the signal.