# US 12,002,406 B2 · Shift register, method for driving shift register, gate driving circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,406 B2 - Document ID: US12002406B2 - Status: Granted - Kind: B2 - Application number: 18/321,717 - Filed: 2023-05-22 - Published: 2023-09-14 - Granted: 2024-06-04 - Earliest claimed: 2023-03-27 - Assignees: Wuhan Tianma Microelectronics Co., Ltd. - Applicants: Wuhan Tianma Microelectronics Co., Ltd. - Inventors: Suping Xi - Web page: https://patentgrep.com/patent/US12002406B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3677: {suitable for active matrices only} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A shift register, a method for driving a shift register, a gate driving circuit and a display panel are provided. The shift register includes: a first output device, where a control terminal thereof is electrically connected to a first node, a first terminal thereof is electrically connected to a first clock signal terminal, and a second terminal thereof is electrically connected to an output terminal of the shift register; a first node control device including a first switch device and a second switch device, where the first switch device is electrically connected to the first node, a first power supply voltage signal terminal and a second node, and the second switch device is electrically connected to the second node, the first power supply voltage signal terminal and the first node. ## Claims ### Claim 1 A shift register, comprising: a first output device, wherein a control terminal of the first output device is electrically connected to a first node, a first terminal of the first output device is electrically connected to a first clock signal terminal, and a second terminal of the first output device is electrically connected to an output terminal of the shift register; and a first node control device comprising a first switch device and a second switch device, wherein a control terminal of the first switch device is electrically connected to the first node, a first terminal of the first switch device is electrically connected to a first power supply voltage signal terminal, a second terminal of the first switch device is electrically connected to a second node; a control terminal of the second switch device is electrically connected to the second node, a first terminal of the second switch device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second switch device is electrically connected to the first node, wherein in a low level output phase, the first switch device is configured to be switched on under control of the first node and write a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is configured to be switched off under control of the second node. ### Claim 2 (depends on 1) The shift register according to claim 1, wherein the first node control device further comprises a third switch device electrically connected to the second node; wherein in a high level output phase, the third switch device is configured to write a turn-on level into the second node, and the second switch device is configured to be switched on under control of the second node and write the cut-off level of the first power supply voltage signal terminal into the first node. ### Claim 3 (depends on 2) The shift register according to claim 2, wherein both a control terminal and a first terminal of the third switch device are electrically connected to a second power supply voltage signal terminal, and a second terminal of the third switch device is electrically connected to the second node; wherein in the high level output phase, the third switch device is configured to be switched on under control of the second power supply voltage signal terminal, and write a turn-on level of the second power supply voltage signal terminal into the second node. ### Claim 4 (depends on 3) The shift register according to claim 3, wherein each of the first switch device and the third switch device comprises a transistor, and an aspect ratio of a channel region of the first switch device is greater than an aspect ratio of a channel region of the third switch device. ### Claim 5 (depends on 4) The shift register according to claim 4, wherein a ratio of the aspect ratio of the channel region of the first switch device to the aspect ratio of the channel region of the third switch device is greater than or equal to 2. ### Claim 6 (depends on 2) The shift register according to claim 2, wherein a control terminal of the third switch device is electrically connected to a second power supply voltage signal terminal, a first terminal of the third switch device is electrically connected to a second clock signal terminal, and a second terminal of the third switch device is electrically connected to the second node; wherein in the high level output phase, the third switch device is configured to be switched on under control of the second power supply voltage signal terminal and write a turn-on level of the second clock signal terminal into the second node. ### Claim 7 (depends on 6) The shift register according to claim 6, wherein in the low level output phase, the third switch device is configured to be switched on under control of the second power supply voltage signal terminal, and write a cut-off level of the second clock signal terminal into the second node. ### Claim 8 (depends on 2) The shift register according to claim 2, wherein a control terminal of the third switch device is electrically connected to a second clock signal terminal, a first terminal of the third switch device is electrically connected to a second power supply voltage signal terminal, and a second terminal of the third switch device is electrically connected to the second node; wherein in the high level output phase, the third switch device is configured to be switched on under control of the second clock signal terminal, and write a turn-on level of the second power supply voltage signal terminal into the second node. ### Claim 9 (depends on 8) The shift register according to claim 8, wherein in the low level output phase, the third switch device is configured to be switched off under control of the second clock signal terminal. ### Claim 10 (depends on 1) The shift register according to claim 1, further comprising: a first switch device, wherein a control terminal of the first switch device is electrically connected to a second power supply voltage signal terminal, a first terminal of the first switch device is electrically connected to the first node, and a second terminal of the first switch device is electrically connected to the control terminal of the first output device. ### Claim 11 (depends on 1) The shift register according to claim 1, wherein the first node control device further comprises a fourth switch device, a control terminal of the fourth switch device is electrically connected to a third cock signal terminal, a first terminal of the fourth switch device is electrically connected to an input terminal of the shift register, a second terminal of the fourth switch device is electrically connected to the first node, and the fourth switch device is configured to write a turn-on level or a cut-off level of the input terminal of the shift register into the first node under control of a third clock signal terminal. ### Claim 12 (depends on 11) The shift register according to claim 11, wherein the fourth switch device comprises a first sub-transistor and a second sub-transistor connected in series, both a gate of the first sub-transistor and a gate of the second sub-transistor are electrically connected to the third clock signal terminal, a first pole of the first sub-transistor is electrically connected to the input terminal of the shift register, a second pole of the first sub-transistor is electrically connected to a first pole of the second sub-transistor, and a second pole of the second sub-transistor is electrically connected to the first node. ### Claim 13 (depends on 1) The shift register according to claim 1, further comprising: a first coupling device, wherein a first terminal of the first coupling device is electrically connected to an output terminal of the shift register, and a second terminal of the first coupling device is electrically connected to the control terminal of the first output device; a second output device, wherein a control terminal of the second output device is electrically connected to a third node, a first terminal of the second output device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second output device is electrically connected to an output terminal of the shift register; and a third node control device comprising a fifth switch device and a sixth switch device, wherein a control terminal of the fifth switch device is electrically connected to the first node, a first terminal of the fifth switch device is electrically connected to a third clock signal terminal, a second terminal of the fifth switch device is electrically connected to the third node, a control terminal of the sixth switch device is electrically connected to the third clock signal terminal, a first terminal of the sixth switch device is electrically connected to a second power supply voltage signal terminal, and a second terminal of the sixth switch device is electrically connected to the third node. ### Claim 14 (depends on 13) The shift register according to claim 13, further comprising: a first storage device, wherein a first terminal of the first storage device is electrically connected to the output terminal of the shift register, and a second terminal of the first storage device is electrically connected to the control terminal of the second output device. ### Claim 15 (depends on 1) A method for driving a shift register, wherein the shift register is the shift register according to claim 1, and the method comprises: providing a turn-on level to the first node in the low level output phase, wherein the first switch device is switched on under control of the first node and writes a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is switched off under control of the second node. ### Claim 16 (depends on 15) The method according to claim 15, wherein the first node control device further comprises a third switch device electrically connected to the second node, and the method further comprises: controlling the third switch device to write a turn-on level into the second node in a high level output level, wherein the second switch device is switched on under control of the second node, and writes a cut-off level of the first power supply voltage signal terminal into the first node. ### Claim 17 (depends on 16) The method according to claim 16, wherein the first node control device further comprises a fourth switch device, a control terminal of the fourth switch device is electrically connected to a third clock signal terminal, a first terminal of the fourth switch device is electrically connected to an input terminal of the shift register, and a second terminal of the fourth switch device is electrically connected to the first node; wherein the shift register further comprises: a second output device, wherein a control terminal of the second output device is electrically connected to a third node, a first terminal of the second output device is electrically connected to the first power supply voltage signal terminal, a second terminal of the second output device is electrically connected to an output terminal of the shift register; a third node control device comprising a fifth switch device and a sixth switch device, wherein a control terminal of the fifth switch device is electrically connected to the first node, a first terminal of the fifth switch device is electrically connected to a third clock signal terminal, and a second terminal of the fifth switch device is electrically connected to the third node; a control terminal of the sixth switch device is electrically connected to the third clock signal terminal, a first terminal of the sixth switch device is electrically connected to a second power supply voltage signal terminal, and a second terminal of the sixth switch device is electrically connected to the third node; a first coupling device, wherein a first terminal of the first coupling device is electrically connected to an output terminal of the shift register, and a second terminal of the first coupling device is electrically connected to the control terminal of the first output device; and a first storage device, wherein a first terminal of the first storage device is electrically connected to the output terminal of the shift register, and a second terminal of the first storage device is electrically connected to the control terminal of the second output device; wherein a high level output phase comprises a first high level output phase before the low level output phase, and the method further comprises: in the first high level output phase, providing a turn-on level to the third clock signal terminal and the input terminal of the shift register, and providing a cut-off level to the first clock signal terminal, wherein the fourth switch device is switched on in response to the turn-on level of the third clock signal terminal and writes a turn-on level of the input terminal of the shift register into the first node; the first output device is switched on in response to the turn-on level of the first node and transmits a high level of the first clock signal terminal to the output terminal of the shift register; the fifth switch device is switched on in response to the turn-on level of the first node and transmits the turn-on level of the third clock signal terminal to the third node; and the second output device is switched on in response to a turn-on level of the third node, and transmits a high level of the first power supply voltage signal terminal to the output terminal of the shift register. ### Claim 18 (depends on 17) The method according to claim 17, wherein the high level output phase further comprises at least one of a second high level output phase, a third high level output phase and a fourth high level output phase after the low level output phase, and the method comprises: In the second high level output phase, providing a turn-on level to the third clock signal terminal and providing a cut-off level to a first lock signal terminal and the input terminal of the shift register, wherein the fourth switch device is switched on in response to the turn-on level of the third clock signal terminal and writes the cut-off level of the input terminal of the shift register into the first node; the first output device is switched off in response to a cut-off level of the first node; the sixth switch device is switched on in response to the turn-on level of the third clock signal terminal and transmits a turn-on level of the second power supply voltage signal terminal to the third node; and the second output device is switched on in response to the turn-on level of the third node, and transmits a high level of the first power supply voltage signal terminal to an output terminal of the shift register; in the third high level output level, providing a turn-on level to the first clock signal terminal and providing a cut-off level to the third clock signal terminal and the input terminal of the shift register, wherein the fourth switch device is switched off in response to the cut-off level of the third clock signal terminal; the first coupling device maintains the cut-off level of the first node; the first output device is switched off in response to the cut-off level of the first node; the first storage device maintains the turn-on level of the third node; the second output device is switched on in response to the turn-on level of the third node, and transmits the high level of the first power supply voltage signal terminal to the output terminal of the shift register; and in the fourth high level output level, providing a turn-on level to the third clock signal terminal and providing a cut-off level to the first clock signal terminal and the input terminal of the shift register, wherein the fourth switch device is switched on in response to the turn-on level of the third clock signal terminal and writes the cut-off level of the input terminal of the shift register into the first node; the first output device is switched off in response to the cut-off level of the first node; the first storage device maintains the turn-on level of the third node; and the second output device is switched on in response to the turn-on level of the third node and transmits the high level of the first power supply voltage signal terminal to the output terminal of the shift register. ### Claim 19 A gate driving circuit, comprising: a plurality of cascaded shift registers, comprising: a first output device, wherein a control terminal of the first output device is electrically connected to a first node, a first terminal of the first output device is electrically connected to a first clock signal terminal, and a second terminal of the first output device is electrically connected to an output terminal of the shift register; and a first node control device comprising a first switch device and a second switch device, wherein a control terminal of the first switch device is electrically connected to the first node, a first terminal of the first switch device is electrically connected to a first power supply voltage signal terminal, a second terminal of the first switch device is electrically connected to a second node; a control terminal of the second switch device is electrically connected to the second node, a first terminal of the second switch device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second switch device is electrically connected to the first node, wherein in a low level output phase, the first switch device is configured to be switched on under control of the first node and write a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is configured to be switched off under control of the second node. ### Claim 20 A display panel, comprising: a gate driving circuit, comprising: a plurality of cascaded shift registers, comprising: a first output device, wherein a control terminal of the first output device is electrically connected to a first node, a first terminal of the first output device is electrically connected to a first clock signal terminal, and a second terminal of the first output device is electrically connected to an output terminal of the shift register; and a first node control device comprising a first switch device and a second switch device, wherein a control terminal of the first switch device is electrically connected to the first node, a first terminal of the first switch device is electrically connected to a first power supply voltage signal terminal, a second terminal of the first switch device is electrically connected to a second node; a control terminal of the second switch device is electrically connected to the second node, a first terminal of the second switch device is electrically connected to the first power supply voltage signal terminal, and a second terminal of the second switch device is electrically connected to the first node, wherein in a low level output phase, the first switch device is configured to be switched on under control of the first node and write a cut-off level of the first power supply voltage signal terminal into the second node, and the second switch device is configured to be switched off under control of the second node.