# US 12,002,404 B2 · Scan driver and display device having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,002,404 B2 - Document ID: US12002404B2 - Status: Granted - Kind: B2 - Application number: 18/132,704 - Filed: 2023-04-10 - Published: 2023-08-03 - Granted: 2024-06-04 - Earliest claimed: 2019-05-23 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Kang Nam Kim; Sung Hoon Lim; Woo Geun Lee; Kyu Sik Cho; Jae Beom Choi - Web page: https://patentgrep.com/patent/US12002404B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/0202: Addressing of scan or signal lines - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0295: by monitoring each display pixel - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal. ## Claims ### Claim 1 A scan driver comprising: a plurality of stages, each of which is configured to control a voltage of a first node in response to a first signal of a previous stage and to output a second signal in response to the voltage of the first node, wherein an nth stage, where n is a natural number, from among the plurality of stages comprises: a first transistor coupled between a first terminal configured to receive the first signal and a second node, the first transistor comprising a gate electrode coupled to a second terminal; a capacitor coupled between the second node and a third terminal; a second transistor coupled between the third terminal and a third node, the second transistor comprising a gate electrode coupled to the second node; and a third transistor coupled between the third node and the first node, the third transistor comprising a gate electrode coupled to a fourth terminal. ### Claim 2 (depends on 1) The scan driver of claim 1, wherein each of the first to third transistors comprises an oxide semiconductor transistor. ### Claim 3 (depends on 1) The scan driver of claim 1, wherein the first transistor comprises a first sub-transistor and a second sub-transistor, which are coupled in series to each other. ### Claim 4 (depends on 1) The scan driver of claim 1, wherein the nth stage is configured to store the first signal in the capacitor in response to a third signal supplied to the second terminal, and to transfer a fourth signal supplied to the third terminal to the first node in response to a voltage charged in the capacitor and a fifth signal supplied to the fourth terminal. ### Claim 5 (depends on 4) The scan driver of claim 4, wherein the fourth signal supplied to the third terminal is a gate-on voltage to turn on an oxide semiconductor transistor. ### Claim 6 (depends on 1) The scan driver of claim 1, wherein the nth stage is configured to discharge the first node in response to a start signal supplied to a fifth terminal. ### Claim 7 A display device comprising: a plurality of pixels respectively coupled to lines; and a scan driver comprising a plurality of stages configured to supply a second signal to the lines, wherein each of the stages is configured to control a voltage of a first node in response to a first signal of a previous stage from among the plurality of stages, and to output the second signal in response to the voltage of the first node, and wherein an nth (n is a natural number) stage from among the plurality of stages comprises: a first transistor coupled between a first terminal configured to receive the first signal and a second node, the first transistor comprising a gate electrode coupled to a second terminal; a capacitor coupled between the second node and a third terminal; a second transistor coupled between the third terminal and a third node, the second transistor comprising a gate electrode coupled to the second node; and a third transistor coupled between the third node and the first node, the third transistor comprising a gate electrode coupled to a fourth terminal. ### Claim 8 (depends on 7) The display device of claim 7, wherein the scan driver further comprises a dummy stage configured to provide the first signal to a first stage from among the plurality of stages, and wherein the dummy stage is electrically separated from the lines. ### Claim 9 (depends on 7) The display device of claim 7, wherein the first transistor comprises a first sub-transistor and a second sub-transistor, which are coupled in series to each other.