# US 12,001,887 B2 · Apparatuses, methods, and systems for instructions for aligning tiles of a matrix operations accelerator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,001,887 B2 - Document ID: US12001887B2 - Status: Granted - Kind: B2 - Application number: 17/134,142 - Filed: 2020-12-24 - Published: 2022-06-30 - Granted: 2024-06-04 - Earliest claimed: 2020-12-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Elmoustapha Ould-Ahmed-Vall - Web page: https://patentgrep.com/patent/US12001887B2 ## CPC - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30098: {Register arrangements} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 15/8023: {Two dimensional arrays, e.g. mesh, torus} - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods, and apparatuses relating to one or more instructions for element aligning of a tile of a matrix operations accelerator are described. In one embodiment, a system includes a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate a third two-dimensional matrix from a proper subset of elements of a row or a column of the first two-dimensional matrix and a proper subset of elements of a row or a column of the second two-dimensional matrix and store the third two-dimensional matrix at a destination in the matrix operations accelerator circuit, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode. ## Claims ### Claim 1 An apparatus comprising: a matrix operations accelerator circuit comprising: a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements; and a hardware processor core coupled to the matrix operations accelerator circuit and comprising: a decoder circuit to decode a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate a third two-dimensional matrix from a proper subset of elements of a row or a column of the first two-dimensional matrix and a proper subset of elements of a row or a column of the second two-dimensional matrix and store the third two-dimensional matrix at a destination in the matrix operations accelerator circuit, and the execution circuit of the hardware processor core to execute the decoded instruction according to the opcode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a row of the first two-dimensional matrix and a proper subset of elements of a row of the second two-dimensional matrix. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the single instruction comprises a field that identifies a non-leading element of the row of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the field is an immediate of the single instruction. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a column of the first two-dimensional matrix and a proper subset of elements of a column of the second two-dimensional matrix. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the single instruction comprises a field that identifies a non-leading element of the column of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the field is an immediate of the single instruction. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the destination in the matrix operations accelerator circuit is the first plurality of registers that represented the first two-dimensional matrix. ### Claim 9 A method comprising: decoding, by a decoder circuit of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements, a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to generate a third two-dimensional matrix from a proper subset of elements of a row or a column of the first two-dimensional matrix and a proper subset of elements of a row or a column of the second two-dimensional matrix and store the third two-dimensional matrix at a destination in the matrix operations accelerator circuit; and executing the decoded instruction by the execution circuit of the hardware processor core according to the opcode. ### Claim 10 (depends on 9) The method of claim 9, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a row of the first two-dimensional matrix and a proper subset of elements of a row of the second two-dimensional matrix. ### Claim 11 (depends on 10) The method of claim 10, wherein the single instruction comprises a field that identifies a non-leading element of the row of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 12 (depends on 11) The method of claim 11, wherein the field is an immediate of the single instruction. ### Claim 13 (depends on 9) The method of claim 9, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a column of the first two-dimensional matrix and a proper subset of elements of a column of the second two-dimensional matrix. ### Claim 14 (depends on 13) The method of claim 13, wherein the single instruction comprises a field that identifies a non-leading element of the column of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 15 (depends on 14) The method of claim 14, wherein the field is an immediate of the single instruction. ### Claim 16 (depends on 9) The method of claim 9, wherein the destination in the matrix operations accelerator circuit is the first plurality of registers that represented the first two-dimensional matrix. ### Claim 17 A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising: decoding, by a decoder circuit of a hardware processor core coupled to a matrix operations accelerator circuit comprising a two-dimensional grid of processing elements, a first plurality of registers that represents a first two-dimensional matrix coupled to the two-dimensional grid of processing elements, and a second plurality of registers that represents a second two-dimensional matrix coupled to the two-dimensional grid of processing elements, a single instruction into a decoded instruction, the single instruction including a first field that identifies the first two-dimensional matrix, a second field that identifies the second two-dimensional matrix, and an opcode that indicates an execution circuit of the hardware processor core is to generate a third two-dimensional matrix from a proper subset of elements of a row or a column of the first two-dimensional matrix and a proper subset of elements of a row or a column of the second two-dimensional matrix and store the third two-dimensional matrix at a destination in the matrix operations accelerator circuit; and executing the decoded instruction by the execution circuit of the hardware processor core according to the opcode. ### Claim 18 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a row of the first two-dimensional matrix and a proper subset of elements of a row of the second two-dimensional matrix. ### Claim 19 (depends on 18) The non-transitory machine readable medium of claim 18, wherein the single instruction comprises a field that identifies a non-leading element of the row of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 20 (depends on 19) The non-transitory machine readable medium of claim 19, wherein the field is an immediate of the single instruction. ### Claim 21 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the opcode indicates the execution circuit of the hardware processor core is to cause the matrix operations accelerator circuit to generate the third two-dimensional matrix from a proper subset of elements of a column of the first two-dimensional matrix and a proper subset of elements of a column of the second two-dimensional matrix. ### Claim 22 (depends on 21) The non-transitory machine readable medium of claim 21, wherein the single instruction comprises a field that identifies a non-leading element of the column of the first two-dimensional matrix that is to be a first element of the third two-dimensional matrix. ### Claim 23 (depends on 22) The non-transitory machine readable medium of claim 22, wherein the field is an immediate of the single instruction. ### Claim 24 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the destination in the matrix operations accelerator circuit is the first plurality of registers that represented the first two-dimensional matrix. ### Claim 25 (depends on 17) The non-transitory machine readable medium of claim 17, the method further comprising translating the single instruction into one or more instructions of a different instruction set architecture prior to the decoding, wherein executing of the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing of the decoded instruction according to the opcode.